Receive Data FIFO Reset Register (RDFR) - 4.3 English

AXI4-Stream FIFO LogiCORE IP Product Guide (PG080)

Document ID
PG080
Release Date
2023-11-08
Version
4.3 English

The Receive Data FIFO Reset Register shown in is not an actual register but, rather a write-only address, which when written with a specific value, generates a reset for the Receive Data FIFO.

This reset does not occur until the receive activity on the RX AXI4-Stream has completed. Only during inactive times on the RX AXI4-Stream can a reset occur. It affects only the receive circuitry in this core. This prevents the core on the other end of the AXI4-Stream from transmitting a partial packet which can cause failure condition in that core. The reset is applied only during the inactive times on the RX AXI4-Stream. Writing a RDFR register with other than A5 value disables the reset.

Because of this mode of operation, it is possible that if the AXI4-Stream interface becomes unresponsive during an AXI4-Stream transaction, that the reset does not occur. For example, if a packet is received over the AXI4-Stream that exceeds the FIFO size of this core, the core destination is ready to become inactive in the middle of a transfer. In this case, an S_AXI_ARESETN reset is needed.

Figure 1. Receive Data FIFO Reset Register (Offset 0x18)
Table 1. Receive Data FIFO Reset Register Bit Definitions
Bit(s) Name Core Access Reset Value Description
31:0 Reset Key Write N/A

Reset Write Value :

"0x000000A5" - Generate a reset.

Others - No effect.