The Receive Data FIFO Data Read Port shown in the following figure is a N-bit wide address location for reading data from the Receive Data FIFO. N is equal to C_S_AXI_DATA_WIDTH.
Important: The value of this register is not guaranteed if
this register is read when Receive Packet Underrun Error (RPUE) interrupt bit in Interrupt
Status Register (ISR) is set.
Figure 1. Receive Data FIFO Data Read Port (Offset 0x20)