Protocol Description - 4.3 English

AXI4-Stream FIFO LogiCORE IP Product Guide (PG080)

Document ID
PG080
Release Date
2023-11-08
Version
4.3 English

The AXI4-Stream FIFO core uses the industry standard AMBA® AXI4-Stream and AXI4 Protocol Specification. The following image details the AXI4-Stream interface where INFORMATION represents all AXI4-Stream signals except TVALID/TREADY.

Figure 1. AXI4-Stream Interface Timing Diagram
Figure 2. AXI4 Write Burst Transaction
Figure 3. AXI4 Read Burst Transaction

This section describes the operation of the AXI4-Stream FIFO core through register accesses using the AXI Ethernet core as an example.

Depending on the Data Interface Option, either AXI4 or AXI4-Lite is used for FIFO accesses. When AXI4-Lite is selected, register access and FIFO accesses are handled by the AXI4-Lite interface. When AXI4 is selected, register access is handled by AXI4-Lite interface and FIFO accesses are handled by AXI4 interface. Data bursting is possible when the Data Interface option is AXI4.

The AXI4-Stream FIFO supports two packet transmission modes: store-and-forward mode and cut-through mode.

  • In store-and-forward mode, packet transmission begins on the AXI4-Stream interface in the following circumstances:
    • When the complete packet is written to the FIFO.
    • When the length of packet is written to TX Length Register.

In this mode, the size of the FIFO must be large enough to hold the complete packet.

In cut-through mode, packet transmission begins on the AXI4-Stream interface when there is enough data in the FIFO. In this mode, the FIFO does not need to hold the complete packet. However, ensure that the AXI4-Stream interface does not under run.

The AXI4-Stream FIFO core supports two packet receiving modes: store-and-forward mode and cut-through mode.

  • In store-and-forward mode, the data from the AXI4-Stream interface is completely stored in the FIFO prior to making it available over the AXI4 interface. The RX Length Register (RLR) is updated with the length of packet, and the interrupt status registers are updated.
  • In cut-through mode, packet reception begins on the AXI4 interface when there is enough data in the FIFO. In this mode, the FIFO does not need to hold the complete packet. The RX Length Register (RLR) register is updated with the data count continuously until the packet is completely received. The RLR register value can be used to read the data out of the FIFO. The cut-through mode supports reception of packets that are larger than the FIFO size. However, ensure that AXI4-Stream interface does not over-run the FIFO.
Note: The AXI4-Stream signal tlast along with tvalid denotes the end of packet in store-and-forward mode and cut-through mode.
Note: The IP is designed to hold a maximum of (RX FIFO depth / 4) + 2 one word packets. For example, if the RX FIFO depth is 512, then the IP can hold a maximum of 130 one word packets.