Port Descriptions - 4.3 English

The AXI4-Stream FIFO core has three AXI4-Stream interfaces: one for transmitting data, one for transmit control, and one for receiving data.

When using the AXI4-Stream FIFO core with the AXI Ethernet core, connect the three AXI4-Stream interfaces listed:

AXI_STR_TXD – AXI4-Stream Transmit Data
AXI_STR_TXC – AXI4-Stream Transmit Control
AXI_STR_RXD – AXI4-Stream Receive Data

The AXI4-Stream Transmit Control Interface supports the transmit protocol of AXI Ethernet cores. The AXI4-Stream Transmit Control Interface is used by the AXI Ethernet core for partial CSUM off-loading of extended VLAN features. The AXI4-Stream FIFO core does not support any advanced features and drives constant values on this interface. The AXI4-Stream FIFO core follows the handshake requirements as defined by the AXI Ethernet Core. For more details, see the AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138).

The AXI4-Stream FIFO core uses one clock from the AXI4-Lite interface for all clock inputs. When the AXI Ethernet core is used with the AXI4-Stream FIFO core, all the AXI4-Stream input clocks of the AXI Ethernet core must use the same clock.

Table 1. I/O Signals
Signal Name	I/O	Width	Default	Description
Top-Level System Signal
Interrupt	O	1	0	Indicates Interrupt status. This signal is asserted if any of the interrupt status bit is set to 1 and interrupt is enabled for that particular bit. By default, the signal is set to 0.
Global Signals
s_axi_aclk	I	1	0	Global Interface Clock: All signals on Interface must be synchronous to ACLK.
s_axi_aresetn	I	1	0	Global reset: This signal is active-Low, ARESETN must be asserted at least for one clock cycle.
AXI4-Lite Write Address Channel Signals
s_axi_awaddr	I	C_S_AXI_ ADDR_WIDTH	0	Write Address: The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
s_axi_awvalid	I	1	0	Write Address Valid: Indicates that valid write address and control information are available: 1 = Address and control information available. 0 = Address and control information not available. The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
s_axi_awready	O	1	0	Write Address Ready: Indicates that the slave is ready to accept an address and associated control signals: 1 = Slave ready 0 = Slave not ready
AXI4-Lite Write Data Channel Signals
s_axi_wdata	I	C_S_AXI_DATA_ WIDTH	0	Write Data: The write data bus width is 32-bit only.
s_axi_wstrb	I	C_S_AXI_DATA_ WIDTH / 8	0	Write Strobes: Indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus. Therefore, WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8 × n)]. For example: S_AXI_WSTRB[0] = 1, WDATA[7:0] is valid. S_AXI_WSTRB[3] = 0b, WDATA[31:24] is not valid.
s_axi_wvalid	I	1	0	Write Valid: Indicates that valid write data and strobes are available: 1 = Write data and strobes available 0 = Write data and strobes not available
s_axi_wready	O	1	0	Write Ready: Indicates that the slave can accept the write data: 1 = Slave ready 0 = Slave not ready
AXI4-Lite Write Response Channel Signals
s_axi_bresp	O	2	0	Write Response: Indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
s_axi_bvalid	O	1	0	Write Response Valid: Indicates that a valid write response is available: 1 = Write response available 0 = Write response not available
s_axi_bready	I	1	1	Response Ready: Indicates that the master can accept the response information. 1 = Master ready 0 = Master not ready
AXI4-Lite Read Address Channel Signals
s_axi_araddr	I	C_S_AXI_ADDR_WIDTH	0	Read Address: The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is provided and the control signals that are issued alongside the address detail how the address is calculated for the remaining transfers in the burst.
s_axi_arvalid	I	1	0	Read Address Valid: When High, indicates that the read address and control information is valid and it remains stable until the address acknowledge signal, ARREADY, is High. 1 = Address and control information valid 0 = Address and control information not valid
s_axi_arready	O	1	0	Read Address Ready: Indicates that the slave is ready to accept an address and associated control signals: 1 = Slave ready 0 = Slave not ready
AXI4-Lite Read Data Channel Signals
s_axi_rdata	O	C_S_AXI_DATA_ WIDTH	0	Read Data: The read data bus width is 32-bit only.
s_axi_rresp	O	2	0	Read Response: Indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
s_axi_rvalid	O	1	0	Read Valid: Indicates that the required read data is available and the read transfer can complete: 1 = Read data available 0 = Read data not available
s_axi_rready	I	1	0	Read Ready: Indicates that the master can accept the read data and response information: 1 = Master ready 0 = Master not ready
AXI4-Stream Transmit Data Channel Signals
axi_str_txd_aclk	I	1	0	ACLK: Clock for the AXI4-Stream Transmit data interface. Presently not used in the core.
mm2s_prmry_reset_out_n	O	1	0	Reset: Reset for the AXI4-Stream Transmit data interface.
axi_str_txd_tvalid	O	1	0	TVALID: Indicates that the master is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted.
axi_str_txd_tready	I	1	0	TREADY: Indicates that the slave can accept a transfer in the current cycle.
axi_str_txd_tdata	O	C_S_AXI_DATA_ WIDTH Or C_S_AXI4_ DATA_WIDTH	0	TDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes. Supported TDATA widths include: 32, 64, 128, 256 or 512 (AXI4 interface only).
axi_str_txd_tkeep	O	C_S_AXI_DATA_ WIDTH/8 Or C_S_AXI4_ DATA_WIDTH/8	0	TKEEP: The byte qualifier that indicates whether the content of the associated byte of TDATA is valid. For a 32-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 3 corresponds to the most significant byte.
axi_str_txd_tlast	O	1	0	TLAST: Indicates the boundary of a packet.
axi_str_txd_tdest	O	C_AXIS_TDEST_ WIDTH	0	TDEST: Destination AXI4-Stream Identifier and provides routing information for the data stream.
axi_str_txd_tstrb	O	C_S_AXI_DATA_ WIDTH/8 Or C_S_AXI4_DATA_WIDTH/8	0	TSTRB: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
axi_str_txd_tid	O	C_AXIS_TID_ WIDTH	0	TID: The data stream identifier that indicates different streams of data.
axi_str_txd_tuser	O	C_AXIS_TUSER_ WIDTH	0	TUSER: User-defined sideband information that can be transmitted with the data stream.
AXI4-Stream Transmit Control Channel Signals
axi_str_txc_aclk	I	1	0	ACLK: Clock for the AXI4-Stream Transmit data interface. Presently not used in the core.
mm2s_cntrl_reset_out_n	O	1	0	Reset: Reset for the AXI4-Stream Transmit data interface.
axi_str_txc_tvalid	O	1	0	TVALID: Indicates that the master is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted
axi_str_txc_tready	I	1	0	TREADY: Indicates that the slave can accept a transfer in the current cycle
axi_str_txc_tdata	O	C_S_AXI_DATA_ WIDTH Or C_S_AXI4_ DATA_WIDTH	0	TDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes. Supported TDATA widths include 32, 64, 128, 256, or 512 (AXI4 Interface only).
axi_str_txc_tkeep	O	C_S_AXI_DATA_ WIDTH/8 Or C_S_AXI4_ DATA_WIDTH/8	0	TKEEP: The byte qualifier that indicates whether the content of the associated byte of TDATA is valid. For a 32-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 3 corresponds to the most significant byte.
axi_str_txc_tlast	O	1	0	TLAST: Indicates the boundary of a packet.
axi_str_txc_tstrb	O	C_S_AXI_DATA_ WIDTH/8 Or C_S_AXI4_DATA_WIDTH/8	0	TSTRB: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
axi_str_txc_tid	O	C_AXIS_TID_ WIDTH	0	TID: The data stream identifier that indicates different streams of data.
axi_str_txc_tdest	O	C_AXIS_TDEST_ WIDTH	0	TDEST: Provides routing information for the data stream.
axi_str_txc_tuser	O	C_AXIS_TUSER_ WIDTH	0	TUSER: User-defined sideband information that can be transmitted with the data stream
AXI4-Stream Receive Data Channel Signals
axi_str_rxd_aclk	I	1	0	ACLK: Clock for the AXI4-Stream Transmit data interface. Presently not used in the core.
s2mm_prmry_reset_out_n	O	1	0	Reset: Reset for the AXI4-Stream Transmit data interface.
axi_str_rxd_tvalid	I	1	0	TVALID: Indicates that the master is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted.
axi_str_rxd_tready	O	1	0	TREADY: Indicates that the slave can accept a transfer in the current cycle.
axi_str_rxd_tdata	I	C_S_AXI_DATA_ WIDTH Or C_S_AXI4_ DATA_WIDTH	0	TDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes. Supported TDATA widths include 32, 64, 128, 256, or 512 (AXI4 interface only).
axi_str_rxd_tkeep	I	C_S_AXI_DATA_ WIDTH/8 Or C_S_AXI4_ DATA_WIDTH/8	0	TKEEP: The byte qualifier that indicates whether the content of the associated byte of TDATA is valid. For a 32-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 3 corresponds to the most significant byte.
axi_str_rxd_tlast	I	1	0	TLAST: Indicates the boundary of a packet.
axi_str_rxd_tdest	I	C_AXIS_TDEST_ WIDTH	0	TDEST: Destination AXI4-Stream Identifier and provides routing information for the data stream.
axi_str_rxd_tstrb¹	O	C_S_AXI_DATA_ WIDTH/8 Or C_S_AXI4_DATA_WIDTH/8	0	TSTRB: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
axi_str_rxd_tid¹	O	C_AXIS_TID_ WIDTH	0	TID: The data stream identifier that indicates different streams of data.
axi_str_rxd_tuser¹	O	C_AXIS_TUSER_ WIDTH	0	TUSER: User-defined sideband information that can be transmitted with the data stream.
AXI4 Write Address Channel Signals
s_axi4_awid	I	C_S_AXI_ID_WIDTH	0	Write Address ID: Identification tag for the write address group of signals.
s_axi4_awaddr	I	C_S_AXI_ADDR_ WIDTH	0	Write Address: The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
s_axi4_awlen	I	8	0	Burst Length: The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
s_axi4_awsize	I	3	0	Burst Size: Indicates the size of each transfer in the burst.
s_axi4_awburst	I	2	0	Burst Type: The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated. This core supports incremental burst type only. Core behavior is not guaranteed if unsupported burst type is set.
s_axi4_awlock	I	1	0	Lock Type: This signal provides additional information about the atomic characteristics of the transfer. Presently this signal is not used in the core.
s_axi4_awcache	I	4	0	Cache Type: Indicates the bufferable, cacheable, writethrough, write-back, and allocate attributes of the transaction. Presently this signal is not used in the core.
s_axi4_awprot	I	3	0	Protection Type: Indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access. Presently this signal is not used in the core.
s_axi4_awvalid	I	1	0	Write Address Valid: Indicates that valid write address and control information are available: 1 = Address and control information available 0 = Address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
s_axi4_awready	O	1	0	Write Address Ready: Indicates that the slave is ready to accept an address and associated control signals: 1 = Slave ready 0 = Slave not ready
AXI4 Write Data Channel Signals
s_axi4_wdata	I	C_S_AXI4_DAT_ WIDTH	0	Write Data: The write data bus can be 32 or 64 bits wide.
s_axi4_wstrb	I	C_S_AXI4_ DATA_WIDTH/8	0	Write Strobes: Indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus. Therefore, WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8 × n)]. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] = 0b, DATA[63:56] is not valid
s_axi4_wlast	I	1	0	Write Last: Indicates the last transfer in a write burst.
s_axi4_wvalid	I	1	0	Write Valid: Indicates that valid write data and strobes are available: 1 = Write data and strobes available 0 = Write data and strobes not available
s_axi4_wready	O	1	0	Write Ready: Indicates that the slave can accept the write data: 1 = Slave ready 0 = Slave not ready
AXI4 Write Response Channel Signals
s_axi4_bid	O	C_S_AXI_ID_ WIDTH	0	Response ID: The identification tag of the write response. The BID value must match the AWID value of the write transaction to which the slave is responding.
s_axi4_bresp	O	2	0	Write Response: Indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
s_axi4_bvalid	O	1	0	Write Response Valid: Indicates that a valid write response is available: 1 = Write response available. 0 = Write response not available.
s_axi4_bready	I	1	1	Response Ready: Indicates that the master can accept the response information. 1 = Master ready. 0 = Master not ready.
AXI4 Read Address Channel Signals
s_axi4_arid	I	C_S_AXI_ID_ WIDTH	0	Read Address ID: This signal is the identification tag for the read address group of signals. ARID is always set to zero; all configured channels access to a single address MAP region in Memory mapped interconnect.
s_axi4_araddr	I	C_S_AXI_ADDR_WIDTH	0	Read Address: The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is provided and the control signals that are issued alongside the address detail how the address is calculated for the remaining transfers in the burst.
s_axi4_arlen	I	8	0	Burst Length: The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
s_axi4_arsize	I	3	0	Burst Size: This signal indicates the size of each transfer in the burst. Burst Size is always set based on configured data width of the interface.
s_axi4_arburst	I	2	0	Burst Type: The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated. Burst Type is always set to Incremental. Core behavior is not guaranteed if unsupported burst type is set.
s_axi4_arlock	I	1	0	Lock Type: This signal provides additional information about the atomic characteristics of the transfer. Presently this signal is not used in the core.
s_axi4_arcache	I	4	0	Cache Type: This signal provides additional information about the cacheable characteristics of the transfer. Presently this signal is not used in the core.
s_axi4_arprot	I	3	0	Protection Type: This signal provides protection unit information for the transaction. Presently this signal is not used in the core.
s_axi4_arvalid	I	1	0	Read Address Valid: When High, indicates that the read address and control information is valid and it remains stable until the address acknowledge signal, ARREADY, is High. 1 = Address and control information valid 0 = Address and control information not valid
s_axi4_arready	O	1	0	Read Address Ready: Indicates that the slave is ready to accept an address and associated control signals: 1 = Slave ready 0 = Slave not ready
AXI4 Read Data Channel Signals
s_axi4_rid	O	C_S_AXI_ID_ WIDTH	0	Read ID Tag: ID tag of the read data group of signals. The RID value is generated by the slave and must match the ARID value of the read transaction to which it is responding.
s_axi4_rdata	O	C_S_AXI4_DATA_WIDTH	0	Read Data: The read data bus can be 32 or 64 bits wide.
s_axi4_rresp	O	2	0	Read Response: Indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
s_axi4_rlast	O	1	0	Read Last: Indicates the last transfer in a read burst.
s_axi4_rvalid	O	1	0	Read Valid: Indicates that the required read data is available and the read transfer can complete: 1 = Read data available 0 = Read data not available
s_axi4_rready	I	1	0	Read Ready: Indicates that the master can accept the read data and response information: 1 = Master ready 0 = Master not ready
This port is currently not used.