Performance - 4.3 English - PG080

To measure the performance (F_MAX) of the AXI4-Stream FIFO core, it was added as the Device Under Test (DUT) to an AMD Virtex™ 7 FPGA as shown in the following figure.

Because the core is used without other design modules in the FPGA, the utilization and timing numbers reported in this section are estimates only. When this core is combined with other designs in the system, the utilization of FPGA resources and timing of the design can vary from the results reported here.

Maximum Frequencies

When targeting Virtex 7 devices, the AXI4-Stream FIFO core can operate up to 300 MHz with the following configuration:

• Data Interface Option: AXI4
• AXI4 Data Width: 64
• Transmit/Receive FIFO Depth: 4096 locations

The F_MAX is influenced by the exact system and provided for guidance. It is not a guaranteed value across all systems.

Latency

Depending on the configuration of the core, the latency between AXI4 to AXI4-Stream varies. For example, if the core is configured for store and forward mode, AXI4-Stream transactions might not start until the entire packet is written into the Transmit FIFO from the AXI4-Lite/AXI4 interface. If the core is configured for TX cut-through/RX cut-through mode, the AXI4-Stream transactions start three clocks after WDATA is accepted from the AXI4-Lite/AXI4 interface.

Throughput

The throughput varies depending on the configuration of the AXI4-Stream FIFO core. For example, if the Data Interface is configured as AXI4-Lite, the throughput is less because the core can accept WDATA once in three clock cycles. If the Data Interface is configured as AXI4, the throughput is three times more than the AXI4-Lite interface. The following table shows the throughput numbers for store-and-forward mode and cut-through mode. Clock frequency is kept constant at 100 MHz to calculate the throughput.