Interrupt Status Register (ISR) - 4.3 English

AXI4-Stream FIFO LogiCORE IP Product Guide (PG080)

Document ID
PG080
Release Date
2023-11-08
Version
4.3 English

The Interrupt Status Register is shown in the following figure. The Interrupt Status register uses one bit to represent each internal interruptible condition.

After an interruptible condition occurs, it is captured in this register (represented as the corresponding bit being set to 1) even if the condition changes. The latched interruptible condition is cleared by writing a 1 to its bit location. Writing a 1 to a bit location that is 0 has no effect. Likewise, writing a 0 to a bit location that is 1 has no effect. Multiple bits can be cleared in a single write.

For any bit set in the Interrupt Status Register, a corresponding bit must also be set in the Interrupt Enable Register for the Interrupt signal to be driven active-High out of the AXI4-Stream FIFO core.

Figure 1. Interrupt Status Register (Offset 0x0)

The Interrupt Status Register bit definitions are detailed in the following table.

Table 1. Interrupt Status Register Bit Definitions
Bit(s) Name Core Access Reset Value Description
14:0 Reserved Read 0x0 Reserved: These bits are reserved for future definition and they always return all zeros.
15 RFE1BE

Read/Clear

on Write of 1

0 Receive FIFO ECC 1 bit error: This interrupt is generated when a 1 bit error is detected on RX FIFO.
16 RFE2BE

Read/Clear

on Write of 1

0 Receive FIFO ECC 2 bit error: This interrupt is generated when a 2 bit error is detected on RX FIFO.
17 TFE1BE Read/Clear on Write of 1 0 Transmit FIFO ECC 1 bit error: This interrupt is generated when a 1 bit error is detected on TX FIFO.
18 TFE2BE Read/Clear on Write 1 0 Transmit FIFO ECC 2 bit error: This interrupt is generated when a 2 bit error is detected on TX FIFO.
19 RFPE Read/Clear on Write of 1 0

Receive FIFO Programmable Empty: Generated when the difference between the read and write pointers of the receive FIFO reaches the programmable EMPTY threshold value when the FIFO is being emptied.

0 = No interrupt pending

1 = Interrupt pending

20 RFPF Read/Clear on Write of 1 1

Receive FIFO Programmable Full: This interrupt is generated when the difference between the read and write pointers of the receive FIFO reaches the programmable FULL threshold value.

0 = No interrupt pending

1 = Interrupt pending

21 TFPE Read/Clear on Write of 1 0

Transmit FIFO Programmable Empty: This interrupt is generated when the difference between the read and write pointers of the transmit FIFO reaches the programmable EMPTY threshold value when the FIFO is being emptied.

0 = No interrupt pending

1 = Interrupt pending

For lower values of programmable threshold, this flag can toggle during the initial writes because of First Word Fall Through (FWFT) behavior of FIFO. This flag can toggle even though there are no external reads.

22 TFPF Read/Clear on Write of 1 1

Transmit FIFO Programmable Full: This interrupt is generated when the difference between the read and write pointers of the transmit FIFO reaches the programmable FULL threshold value.

0 = No interrupt pending

1 = Interrupt pending

23 RRC Read/Clear on Write of 1 1

Receive Reset Complete: This interrupt indicates that a reset of the receive logic has completed.

0 = No interrupt pending

1 = Interrupt pending

24 TRC Read/Clear on Write of 1 1

Transmit Reset Complete: This interrupt indicates that a reset of the transmit logic has completed.

0 = No interrupt pending

1 = Interrupt pending

25 TSE Read/Clear on Write of 1 0

Transmit Size Error: This interrupt is generated if the number of words (including partial words in the count) written to the transmit data FIFO does not match the value written to the transmit length register (bytes) divided by 4/8 and rounded up to the higher integer value for trailing byte fractions. Interrupts occur only for mismatch of word count (including partial words). Interrupts do not occur due to mismatch of byte count.

0 = No interrupt pending

1 = Interrupt pending

26 RC Read/Clear on Write of 1 0 Receive Complete: Indicates that at least one successful receive has completed and that the receive packet data and packet data length is available. This signal is not set for unsuccessful receives. This interrupt can represent more than one packet received, so it is important to check the receive data FIFO occupancy value to determine if additional receive packets are ready to be processed.

0 = No interrupt pending

1 = Interrupt pending

27 TC Read/Clear on Write of 1 0

Transmit Complete: Indicates that at least one transmit has completed.

0 = No interrupt pending

1 = Interrupt pending

28 TPOE Read/Clear on Write of 1 0

Transmit Packet Overrun Error: This interrupt is generated if an attempt is made to write to the transmit data FIFO when it is full. A reset of the transmit logic is required to recover.

0 = No interrupt pending

1 = Interrupt pending

29 RPUE Read/Clear on Write of 1 0

Receive Packet Underrun Error: This interrupt occurs when an attempt is made to read the receive FIFO when it is empty. The data read is not valid. A reset of the receive logic is required to recover.

0 = No interrupt pending

1 = Interrupt pending

30 RPORE Read/Clear on Write of 1 0

Receive Packet Overrun Read Error: This interrupt occurs when more words are read from the receive data FIFO than are in the packet being processed. Even though the FIFO is not empty, the read has gone beyond the current packet and removed the data from the next packet. A reset of the receive logic is required to recover.

0 = No interrupt pending

1 = Interrupt pending

31 RPURE Read/Clear on Write of 1 0

Receive Packet Underrun Read Error: This interrupt occurs when an attempt is made to read the receive length register when it is empty. The data read is not valid. A reset of the receive logic is required to recover.

0 = No interrupt pending

1 = Interrupt pending