Interrupt Enable Register (IER) - 4.3 English

AXI4-Stream FIFO LogiCORE IP Product Guide (PG080)

Document ID
PG080
Release Date
2023-11-08
Version
4.3 English

The Interrupt Enable Register shown in determines which interrupt sources in the Interrupt Status Register are allowed to generate interrupts. Setting to “1” in a bit location enables the related interrupt from being propagated, while a value of “0” disables it.

Figure 1. Interrupt Enable Register (Offset 0x4)