| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 |
AMD UltraScale+™ families AMD UltraScale™ families AMD Zynq™ 7000 SoC 7 series FPGAs |
| Supported User Interfaces | AXI4, AXI4-Lite, AXI4-Stream |
| Resources | See Resource Utilization |
| Provided with Core | |
| Design Files | VHDL |
| Example Design | VHDL |
| Test Bench | VHDL |
| Constraints File | Not Provided |
| Simulation Model | Not Provided |
| Supported S/W Driver 2 | Standalone |
| Tested Design Flows 3 | |
| Design Entry | Vivado Design Suite |
| Simulation | For support simulators, see the Vivado Design Suite: Release Notes, Installation and Licensing |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 54447 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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