The AXI4-Stream FIFO core can be used in applications to interface between an AXI4 interface and an AXI4-Stream interface. An example of this application would be the AMD AXI Ethernet IP core which has an AXI4-Lite interface for configuration and control and an AXI4-Stream interface for data transfer. The AXI4-Stream FIFO can be used as a bridge to interface to the AXI4 or AXI4-Lite interfaces as shown in the following figure.
Figure 1. AIX4-Stream FIFO Connected to an AXI Ethernet Core

Design Tools
The AXI4-Stream FIFO core design is implemented using VHDL code. The AMD Vivado™ Design Suite includes a synthesis tool for synthesizing the core.
Target Technology
The target technology is an FPGA listed in the supported device family field of the IP Facts Table.