Cut-Through Mode - 4.3 English

AXI4-Stream FIFO LogiCORE IP Product Guide (PG080)

Document ID
PG080
Release Date
2023-11-08
Version
4.3 English

In this mode, the length is written by the AXI4-Stream FIFO core when the RX FIFO is not empty. Bit 31 of the register is used to indicate whether the length value given in the remaining 30 bits is for a partial or full packet. When bit 31 is 1, the length indicates the amount of partial packet data that can be read. After the last beat of the packet received on the AXI4-Stream side, bit 31 becomes 0 and remaining bits show the complete packet length.

The width of the RLR is wide enough to support packets up to 8 MBytes–4 (8388604) in length. The smallest packet that can be received is 1 byte. The maximum packet that can be received is 8 MBytes–4 and is independent of the RX FIFO depth selected in AMD Vivado™ IDE.

Figure 1. Receive Length Register: Cut-Through Mode (Offset 0x24)
Table 1. Receive Length Register: (Cut-Through Mode) Bit Definitions
Bit(s) Name Core Access Reset Value Description
22:0 RXL Read 0x0 Receive Length : The number of bytes of the corresponding receive data stored in the receive data FIFO.
30:23 Reserved Read 0x0 Reserved : These bits are reserved for future definition and always return all zeros.
31 Partial/Full Packet Length Read 0x0 Partial/Full Packet Length Indicator: When bit 31 is 1, the RXL indicates the amount of partial packet data that can be read. After the last beat of the packet received on the AXI4-Stream side, bit 31 becomes 0 and the RXL shows the complete packet length.