This section includes information about using AMD Adaptive Computing tools to customize and generate the core in the AMD Vivado™ Design Suite. You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
- Select the IP from the IP catalog. The AXI4-Stream FIFO core is located under AXI Infrastructure in the AMD Vivado™ IP catalog.
- Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.
- Data Interface
- AXI4-Lite interface is for register access and transmit/receive FIFO accesses. Supported data width in this mode is 32. In this mode, all register accesses, except transmit/receive data FIFO registers are accessed using the AXI4-Lite interface. Only transmit/receive data FIFO registers are accessed using the AXI4 interface. Data bursting is possible only in the AXI4 mode. The supported data width in this mode is 32, 64, 128, 256, and 512 (only for transmit/receive data FIFO registers).
- AXI4 Data Width
- The AXI4 data width defines the width of the transmit/receive data FIFO registers. Supported data width is 32, 64, 128, 256, and 512.
- AXI4 ID Width
- The AXI4 ID width defines the width of the AWID/BID/ARID/RID ports. Supported ID width is 0 to 32.
- Transmit FIFO
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Enable Transmit Data: Enables the transmit datapath (from AXI4 interface to AXI4-Stream interface).
Enable Transmit Control: Enables the transmit control. The AXI4-Stream Transmit Control Interface supports the transmit protocol of AXI Ethernet cores.
Enable Transmit Cut-Through: Enables the cut-through mode in which packet transmission begins on the AXI4-Stream interface when there is enough data in the FIFO. When this option is not selected, the FIFO operates in Store-and-Forward Mode.
Transmit FIFO Depth: Valid range of the transmit FIFO depth is 512 to 128 k locations (powers of 2).
Transmit FIFO Programmable Full Threshold: The valid range for this threshold is provided in the IDE. When the difference between the read and write pointers of the transmit FIFO reaches the programmable FULL threshold value, the TFPF bit in ISR is set.
Transmit FIFO Programmable Empty Threshold: The valid range for this threshold is provided in the IDE. When the difference between the read and write pointers of the transmit FIFO reaches the programmable EMPTY threshold value, the TFPE bit in ISR is set.
Transmit FIFO Cascade Height: This parameter specifies the number of block RAMs present in one cascade chain of a Transmit FIFO. To implement a memory that requires more than 1 block RAM, it needs to connect several block RAMs using built-in cascade and/or fabric LUTs (MUXes). When cascade_height = 1, synthesis uses NO cascade at all. This is used for maximum timing performance. Default value is 0 (that is, synthesis has an option to choose cascading or not).
Enable ECC for Transmit FIFO: This parameter enables the ECC on Transmit FIFO. If any 1-bit error is detected on Transmit FIFO, TFE1BE (Transmit FIFO ECC 1 Bit Error) bit in the ISR is set. 1-bit error is corrected automatically. Number of 1-bit errors are counted and stored in Transmit FIFO ECC Error Counter register lower 16 bits (for example [15:0]). If any 2-bit error is detected on Transmit FIFO, TFE2BE (Transmit FIFO ECC 2 Bit Error) bit in the ISR is Set and the number of 2-bit errors are counted and stored in Transmit FIFO ECC Error Counter register upper 16 bits (for example [31:16]). The default value is 0.
- Receive FIFO
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Note: The Full and Empty threshold range is different from previous version of the core (v4.1) due to the use of XPM libraries. See the IP catalog GUI for the valid range of values.Enable Receive Data Enables the receive datapath (from AXI4-Stream interface to AXI4 interface).
Enable Receive Cut-Through: Enable Receive Cut-Through: Enables the cut-through mode in which packet reception begins on the AXI4 interface when there is enough data in the FIFO. When this option is not selected, the FIFO operates in Store-and-Forward Mode.
Receive FIFO Depth: Valid range of the receive FIFO depth is 512 to 128 k locations (powers of 2).
Receive FIFO Programmable Full Threshold: The valid range for this threshold is provided in the IDE. When the difference between the read and write pointers of the receive FIFO reaches the programmable FULL threshold value, the RFPF bit in ISR is set.
Receive FIFO Programmable Empty Threshold: The valid range for this threshold is provided in the IDE. When the difference between the read and write pointers of the receive FIFO reaches the programmable EMPTY threshold value, the RFPE bit in ISR is set.
Receive FIFO Cascade Height: This parameter specifies the number of block RAMs present in one cascade chain of a Receive FIFO. To implement a memory that requires more than 1 block RAM, it needs to connect several block RAMs using built-in cascade and/or fabric LUTs (MUXes). When cascade_height = 1, synthesis uses NO cascade at all. This is used for maximum timing performance. Default value is 0 (that is, synthesis has an option to choose cascading or not).
Enable ECC for Receive FIFO: This parameter enables the ECC on Receive FIFO. If any 1-bit error is detected on Receive FIFO, RFE1BE (Receive FIFO ECC 1 Bit Error) bit in the ISR is set. 1-bit error is corrected automatically. Number of 1-bit errors are counted and stored in the Receive FIFO ECC Error Counter register lower 16 bits (for example [15:0]). If any 2-bit error is detected on Receive FIFO, RFE2BE (Receive FIFO ECC 2-Bit Error) bit in the ISR is set and the number of 2-bit errors are counted and stored in Receive FIFO ECC Error Counter register upper 16 bits, for example [31:16]. Default value is 0.
User Parameters
The following table shows the relationship between the GUI fields in the Vivado IDE and the User Parameters (which can be viewed in the Tcl Console).
GUI Parameter/Value | User Parameter/Value | Default Value |
---|---|---|
Component Name | Component_Name | None |
AXI4 ID Width | C_S_AXI_ID_WIDTH | 4 |
Data Interface | C_DATA_INTERFACE_TYPE | AXI4-Lite |
AXI4 Data Width | C_S_AXI4_DATA_WIDTH | 32 |
Transmit FIFO Options | ||
Enable Transmit Data | C_USE_TX_DATA | True: 1 |
Enable Transmit Control | C_USE_TX_CTRL | True: 1 |
Enable Transmit Cut Through | C_USE_TX_CUT_THROUGH | False: 0 |
Transmit FIFO Depth | C_TX_FIFO_DEPTH | 512 |
Transit FIFO Programmable Full Threshold | C_TX_FIFO_PF_THRESHOLD | 507 |
Transmit FIFO Programmable Empty Threshold | C_TX_FIFO_PE_THRESHOLD | 5 |
Transmit FIFO Cascade Height | C_TX_CASCADE_HEIGHT | 0 |
Enable ECC for Transmit FIFO | TX_ENABLE_ECC | 0 |
Receive FIFO Options | ||
Enable Receive Data | C_USE_RX_DATA | True: 1 |
Enable Receive Cut Through | C_USE_RX_CUT_THROUGH | False: 0 |
Receive FIFO Depth | C_RX_FIFO_DEPTH | 512 |
Receive FIFO Programmable Full Threshold | C_RX_FIFO_PF_THRESHOLD | 507 |
Receive FIFO Programmable Empty Threshold | C_RX_FIFO_PE_THRESHOLD | 5 |
Receive FIFO Cascade Height | C_RX_CASCADE_HEIGHT | 0 |
Enable ECC for Receive FIFO | RX_ENABLE_ECC | 0 |
AXI4-Stream Ports | ||
C_HAS_AXIS_TUSER | False: 0 | |
C_HAS_AXIS_TID | False: 0 | |
C_HAS_AXIS_TDEST | False: 0 | |
TID Width | C_AXIS_TID_WIDTH | 4 |
TUSER Width | C_AXIS_TUSER_WIDTH | 4 |
TDEST Width | C_AXIS_TDEST_WIDTH | 4 |
TSTRB | C_HAS_AXIS_TSTRB | False: 0 |
TKEEP | C_HAS_AXIS_TKEEP | False: 0 |
Output Generation
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896).