The following diagram shows the major components of the AXI4-Stream FIFO core:
- AXI Interface block with an AXI4/AXI4-Lite Slave interface
- Interrupt controller
- Registers space
- Receive control module
- Transmit control module
- Receive FIFO for the receive data and length
- Transmit FIFO for the transmit data and the length
Figure 1. AXI4-Stream FIFO Core Block Diagram
Note: Supported data widths for
AXI4_STR_TxC/AXI4_STR_TxD/AXI4_STR_RxD are 32/64/128/256/512 bits.The AXI4-Stream FIFO core was designed to provide memory-mapped access to an AXI4-Stream interface connected to other IP (such as the AXI Ethernet core). Systems must be built through the AMD Vivado™ Design Suite to attach the AXI4-Stream FIFO core, AXI Ethernet core, processor, memory, interconnect the buses, clocking, and additional embedded components.