The AXI4-Stream FIFO core operates on a single clock
(s_axi_aclk), and all input and output interface signals of the AXI4-Stream and AXI4-Lite/AXI4 interfaces are
synchronized with this clock.
The AXI4-Stream FIFO core operates on a single clock
(s_axi_aclk), and all input and output interface signals of the AXI4-Stream and AXI4-Lite/AXI4 interfaces are
synchronized with this clock.