Using Vivado Lab Tools - 12.0 English

The integrated logic analyzer (ILA) and VIO cores aid in debugging and validating the design in the board and are provided with the Aurora 64B/66B core. The Aurora 64B/66B core connects the relevant signals to the VIO to facilitate easier bring-up or debug of the design. Select the Vivado Lab Tools option from the Core Options tab in the Vivado Integrated Design Environment (IDE) (see Figure 1) to include it as a part of the example design.

Cores generated with the Vivado lab tools option enabled have three VIO interfaces and one ILA interface.

1. vio1_inst – contains core Lane Up, Channel Up, Data Error count, Soft Error count, Channel Up transition count along with System Reset, GT Reset, and Loopback ports.
2. vio2_inst – contains status of reset quality counters
3. vio3_inst – contains test pass/fail status for repeat reset test
4. i_ila – contains core status signals like hard_err, soft_err, channel_up, lane_up, and data_err; and the first 16 bits of tx and rx data