User Parameters - 13.0 English - PG074

Aurora 64B/66B LogiCORE IP Product Guide (PG074)
Document ID
PG074
Release Date
2024-12-11
Version
13.0 English

The following table shows the relationship between the fields in the Vivado IDE and the User Parameters in the XCI files (which can be viewed in the Tcl Console). Use the information in the tables for batch-driven Tcl flows to set Vivado IDE parameters and generate the Aurora 64B/66B core.

Table 1. Vivado IDE Parameter to User Parameter Mapping(1)
Vivado IDE Parameter User Parameter Default Value(1)
Core Options
Physical Layer
Line Rate (Gb/s) C_LINE_RATE

3.125/

10.3125
GT Type(11) C_GT_TYPE GTH/GTY
Column Used(11) C_UCOLUMN_USED right
Starting GT Quad(11) C_START_QUAD Quad X0Y0
Starting GT Lane(11) C_START_Lane X0Y0
GT Refclk Selection(13) C_REFCLK_SOURCE MGTREFCLK0 of Quad X0Y0
GT Refclk (MHz)(15) C_REFCLK_FREQUENCY 156.250
INIT clk (MHz) C_INIT_CLK

50.0/

161.1328125
GT DRP clk (MHz)(9) DRP_FREQ 100.0000
Generate Aurora without GT(14) C_GTWIZ_OUT false
Link Layer
Dataflow Mode Dataflow_Config Duplex
Interface Interface_Mode Framing
Flow Control Flow_Mode None
USER-K C_USER_K false
Little Endian Support C_USE_BYTESWAP false
Error Reduction
CRC CRC_MODE NONE
DRP Mode
AXI4-Lite (default mode) drp_mode AXI4_LITE
Native
Vivado lab tools C_USE_CHIPSCOPE false
Additional transceiver control and status ports TransceiverControl false
GT Selections(9)
Columns C_COLUMN_USED right(3)
Lanes(10) C_AURORA_LANES 1
GT Type(10) C_GT_TYPE gtx(4)
Lane Assignment
Select transceiver to include GTXE2_CHANNEL_X1Y4 in your design(5) C_GT_LOC_5(6) 1
Select transceiver to include GTXE2_CHANNEL_X1Y5 in your design C_GT_LOC_6 X
Select transceiver to include GTXE2_CHANNEL_X1Y6 in your design C_GT_LOC_7 X
Select transceiver to include GTXE2_CHANNEL_X1Y7 in your design C_GT_LOC_8 X
Select transceiver to include GTXE2_CHANNEL_X1Y8 in your design C_GT_LOC_9 X
Select transceiver to include GTXE2_CHANNEL_X1Y9 in your design C_GT_LOC_10 X
Select transceiver to include GTXE2_CHANNEL_X1Y10 in your design C_GT_LOC_11 X
Select transceiver to include GTXE2_CHANNEL_X1Y11 in your design C_GT_LOC_12 X
Select transceiver to include GTXE2_CHANNEL_X1Y12 in your design C_GT_LOC_13 X
Select transceiver to include GTXE2_CHANNEL_X1Y13 in your design C_GT_LOC_14 X
Select transceiver to include GTXE2_CHANNEL_X1Y14 in your design C_GT_LOC_15 X
Select transceiver to include GTXE2_CHANNEL_X1Y15 in your design C_GT_LOC_16 X
Select transceiver to include GTXE2_CHANNEL_X1Y16 in your design C_GT_LOC_17 X
Select transceiver to include GTXE2_CHANNEL_X1Y17 in your design C_GT_LOC_18 X
Select transceiver to include GTXE2_CHANNEL_X1Y18 in your design C_GT_LOC_19 X
Select transceiver to include GTXE2_CHANNEL_X1Y19 in your design C_GT_LOC_20 X
GTRefclk (MHz)
GT Refclk1 C_GT_CLOCK_1 GTXQ1
GT Refclk2 C_GT_CLOCK_2 None
Shared Logic
Include Shared Logic in core SupportLevel(8) 0
Include Shared Logic in example design (default mode)
Single Ended INIT CLK(9)(12) SINGLEEND_INITCLK false
Single Ended GTREF CLK(12) SINGLEEND_GTREFCLK false
  1. The values in this table reflect the default device (xc7vx485tffg1157-1). Default values for UltraScale architecture devices are denoted with a slash (/) where appropriate.
  2. X0Y0 GT selection is based on columns.
  3. If a device has transceivers on both sides, left is the default value.
  4. If a 7 series device has GTX transceivers, gtx is the default value. In case of GTH transceivers, v7gth is the default value.
  5. Numbering for the default device starts from GTXE2_CHANNEL_X1Y4. Otherwise, the numbering starts from GTXE2_CHANNEL_X0Y0.
  6. C_GT_LOC_i, where i varies from 1 to 48.
  7. By default, the lowest i C_GT_LOC_i is assigned.
  8. If Shared Logic in Core option is selected, SupportLevel is 1.
  9. Not available in UltraScale devices.
  10. The Lanes and GT Type options for UltraScale devices are available on the Core Options page in the Vivado IDE.
  11. Not available in 7 series devices.
  12. Available if Include Shared Logic in core option is selected.
  13. The GT Refclk selection option is not applicable for line rate > 16.375G core configuration. Defaulted to GTREFCLK0 of each active transceiver Quads reference clocks.
  14. Generate Aurora without GT option is available only for AMD UltraScale™ and AMD UltraScale+™ devices in IP catalog.
  15. Fractional divider option is not supported in GTY based designs.
Recommended: Do not alter any default locations, unless otherwise absolutely needed after the design is generated, or else the design functionality cannot be guaranteed. For UltraScale and UltraScale+ devices based designs, when a line rate of less than 8.0 Gb/s is chosen, the CPLL becomes part of the GT Wizard hierarchical core.