User Interface Ports - 12.0 English

Aurora 64B/66B LogiCORE IP Product Guide (PG074)

Document ID

PG074

Release Date

2023-11-17

Version

12.0 English

Either a framing or a streaming user data interface can generate the Aurora 64B/66B core. Data port width depends on the number of lanes selected. The following table lists simplex/duplex port descriptions for the AXI4-Stream TX data ports.

Table 1. User Interface Ports
Name	Direction	Clock Domain	Description
USER_DATA_S_AXIS_TX
s_axi_tx_tdata[0:(64n –1)] or s_axi_tx_tdata[(64 n –1):0]⁽¹⁾⁽²⁾	Input	user_clk	Outgoing data (ascending bit order).
s_axi_tx_tready⁽²⁾	Output	user_clk	Asserted when signals from the source are accepted. Deasserted when signals from the source are ignored.
s_axi_tx_tvalid⁽²⁾	Input	user_clk	Asserted when AXI4-Stream signals from the source are valid. Deasserted when AXI4-Stream control signals and/or data from the source should be ignored.
s_axi_tx_tlast⁽²⁾	Input	user_clk	Indicates the end of the frame. This port is not available if the Streaming interface option is chosen.
s_axi_tx_tkeep[0:(8 n –1)] or s_axi_tx_tkeep[(8 n –1):0]⁽¹⁾⁽²⁾	Input	user_clk	Specifies the number of valid bytes in the last data beat (number of valid bytes = number of 1s in tkeep). s_axi_tx_tkeep is sampled only when s_axi_tx_tlast is asserted. The core supports continuous aligned and continuous unaligned data streams and expects data to be filled continuously from LSB to MSB. There cannot be invalid bytes interleaved with the valid s_axi_tx_tdata bus. This port is not available if the Streaming interface option is chosen.
USER_DATA_M_AXIS_RX
m_axi_rx_tdata[0:(64 n –1)] or m_axi_rx_tdata[(64 n –1):0]⁽¹⁾ ⁽³⁾	Output	user_clk	Incoming data from channel partner (ascending bit order).
m_axi_rx_tvalid⁽³⁾	Output	user_clk	Asserted when data from the core is valid. Deasserted when data from the core should be ignored.
m_axi_rx_tlast⁽³⁾	Output	user_clk	Indicates the end of the incoming frame. This port is not available if the Streaming interface option is chosen.
m_axi_rx_tkeep[0:(8n –1)] or m_axi_rx_tkeep[(8n –1):0]⁽¹⁾ ⁽³⁾	Output	user_clk	Specifies the number of valid bytes in the last data beat. This port is not available if the Streaming interface option is chosen.
'n' is the number of lanes. The port is not available RX-only simplex mode. The port is not available TX-only simplex mode.