Use Case 3: Assertion of reset_pb in the Simplex Core - 12.0 English

Aurora 64B/66B LogiCORE IP Product Guide (PG074)

Document ID
Release Date
12.0 English

The following figure shows the simplex-TX core and simplex-RX core connected in a system. CONFIG1 and CONFIG2 can be in same or multiple device(s).

Figure 1. System with Simplex Cores

Following is the recommended procedure of TX cores reset and RX cores reset assertion in the simplex core (see the following figure).

  1. The TX cores reset_pb is asserted for a duration not less than 128* user_clk time period followed by reset_pb on the RX simplex core asserted for a duration not less than 128*user_clk time period.
  2. tx_channel_up and rx_channel_up are deasserted after a minimum of five user_clk clock cycles.
  3. The signal reset_pb in the RX simplex core is deasserted (or) released before reset_pb is deasserted in the TX simplex core. This sequence occurs because, while the auto simplex recovery feature allows both boards to be brought up independently, this ensures that TX transmits the Aurora 64B/66B initialization sequence when the simplex-RX core is ready.
  4. rx_channel_up is asserted before tx_channel_up assertion. This condition must be satisfied by the simplex-RX core and the simplex timer parameters (SIMPLEX_TIMER_VALUE) in the simplex-TX core need to be adjusted to meet this criteria. The SIMPLEX_TIMER_VALUE parameter can be updated in <user_component_name>_core.v.
  5. tx_channel_up is asserted after the simplex-TX core completes the Aurora 64B/66B protocol channel initialization sequence transmission for the configured time. Asserting tx_channel_up last ensures that the simplex-TX core transmits an Aurora 64B/66B initialization sequence when the simplex-RX core is ready.
  6. For TX/RX simplex cores, the reset sequence in duplex cores for reset_pb and pma_init assertions can be followed. However, the SIMPLEX_TIMER_VALUE needs to be tuned based on the use model of the core.
Figure 2. Reset Assertion in Simplex Cores