Updates in the v9.0 Core - 12.0 English

Aurora 64B/66B LogiCORE IP Product Guide (PG074)

Document ID
Release Date
12.0 English
  • In the TX Startup FSM, the prior counting mechanism for mmcm_lock_count was based on txuserclk. Limitations resulted because this was a recovered clock. stable_clock is now used for the MMCM Lock synchronization.
  • The RX datapath is now 32 bits up to the CBCC module, thus avoiding width conversion logic and clk_en generation. These functions are handled in the CBCC module before writing data to the FIFO.
  • Logic added to detect polarity inversion and to invert polarity while lane init is enabled.
  • The core internally generates tx_channel_up for Aurora 64B/66B TX logic and rx_channel_up for Aurora 64B/66B RX logic. This action ensures that the RX logic is active and ready to receive before the TX logic begins sending. rx_channel_up is presented as channel_up.
  • Reset and controls are common across all lanes.
  • The RX CDR lock time was increased from 50 KUI to 37 MUI as suggested by the transceiver user guide.
  • The Block Sync header max count was increased from 64 to 60,000 to improve the robustness of the link.
  • Allowed transmission of more idle characters during channel initialization to improve the robustness of the link.
  • Removed the scrambler reset making it free running to achieve faster CDR lock. The default pattern sent by the scrambler is the scrambled value of NA idle character.
  • Updated the GTH transceiver QPLL attributes - See answer record 56332.
  • Added shared logic and optional transceiver control and status debug ports.
  • Updated clock domain crossing synchronizers to increase Mean Time Between Failures (MTBF) from meta-stability. Currently, using a common synchronizer module and applying false path constraints only for the first stage of the flops.
  • Added support for Cadence IES and Synopsys VCS simulators.
  • Added Vivado lab tools support for debugging.
  • Added quality counters in the example design to increase the test quality.
  • Added a hardware reset state machine in the example design to perform repeat reset testing.