The Aurora 64B/66B core samples the data only if both
s_axi_tx_tready and s_axi_tx_tvalid are asserted. The user application can deassert
s_axi_tx_tvalid on any clock cycle (Data
Transfer with Pause) to ignore the AXI4-Stream input
for that cycle. If this occurs in the middle of a frame, idle symbols are sent
through the Aurora 64B/66B channel.The AXI4-Stream data is only valid when it is
framed. Data outside of a frame is ignored. To end a frame, assert s_axi_tx_tlast while the last word (or partial
word) of data is on the s_axi_tx_tdata port
and use s_axi_tx_tkeep to specify the number
of valid bytes in the last data beat.
High priority is assigned to these requests for any type of transfer:
- TXDATAVALID deasserted from the transceiver TX interface (1 cycle)
- CC transmission (8 cycles)