The Aurora 64B/66B top-level (block level) file contains the top-level interface definition and is the starting point for a user design. The top-level file instantiates the Aurora 64B/66B lane module, the TX and RX AXI4-Stream modules, the global logic module, and the GTX, GTH, or GTY transceiver wrapper. This top-level wrapper file is instantiated in the example design file together with the clock, reset circuit, frame generator, and checker modules.
The following figure shows the Aurora 64B/66B top-level for a duplex configuration.
The timing requirements for the streaming and framing interfaces are described in Framing Interface and Streaming Interface below.
The following figure shows an n -byte example of the Aurora 64B/66B AXI4-Stream data interface bit ordering.
