The Aurora 64B/66B core delivers a demonstration test bench for the example design. This chapter describes the Aurora 64B/66B test bench and its functionality. The test bench consists of the following modules:
- Device Under Test (DUT)
- Clock and reset generator
- Status monitor
The Aurora 64B/66B test bench components can change based on the selected Aurora 64B/66B core configurations, but the basic functionality remains the same for all of the core configurations.
The Aurora 64B/66B test bench environment connects the Aurora 64B/66B duplex/TX/RX simplex core in loopback using a high-speed serial interface. The preceding figure shows the Aurora 64B/66B test bench for the duplex/TX/RX simplex configuration.
The test bench looks for the state of the channel, then the
integrity of the user data, UFC data, and user-K blocks for a predetermined simulation time.
The channel_up assertion message indicates that link training and channel
bonding (in case of multi-lane designs) are successful. The counter is maintained in the
FRAME_CHECK module to track the reception of erroneous data. The test bench flags an error
when erroneous data is received.
The Aurora 64B/66B test bench environment connects the Aurora 64B/66B simplex core to the partner simplex Aurora 64B/66B core using the high-speed serial interface. The preceding figure shows the Aurora 64B/66B test bench for the simplex configuration where DUT1 is configured as TX-only simplex and DUT2 is configured as RX-only simplex.
The test bench looks for the state of the transmitter and
receiver channels and then checks the integrity of the user data for a pre-determined
simulation time. The tx_channel_up and rx_channel_up
assertion messages indicate that link training and channel bonding (in case of multi-lane
designs) are successful.