Status, Control, and Transceiver Ports - 12.0 English

Aurora 64B/66B LogiCORE IP Product Guide (PG074)

Document ID
PG074
Release Date
2023-11-17
Version
12.0 English

The status and control ports of the Aurora 64B/66B core allow user applications to monitor the channel and use built-in features of the GTX, GTH, and GTY transceivers. This section provides diagrams and port descriptions for the status and control interface, and the transceiver serial I/O interfaces.

The following table describes the function of the Aurora 64B/66B core status and control ports allowing user applications to monitor the Aurora 64B/66B channel, and access built-in features of the serial transceiver interface. The DRP interface allows reading and updating of the serial transceiver parameters and settings through the AXI4-Lite protocol-compliant or native dynamic reconfiguration port (DRP) interfaces.

Table 1. Transceiver Control and Status Interface Ports
Name Direction Clock Domain Description

reset_pb/

tx_reset_pb/

rx_reset_pb

Input async

Push Button Reset. The top-level reset input at the example design level. Required to drive the Support Reset logic inside the core.

  • reset_pb is available in Duplex, TX-only_simplex and RX-only_simplex modes.
  • tx_reset_pb is available in TX/RX_simplex mode.
  • rx_reset_pb is available in TX/RX_simplex mode.
gt_reset_out Output init_clk Output of de-bouncer for gt_reset. Enabled when Include Shared Logic in Core is selected.

sys_reset_out/

tx_sys_reset_out/

rx_sys_reset_out

Output user_clk

System reset output to be used by the example design level logic.

  • sys_reset_out is available in Duplex, TX-only_simplex and RX-only_simplex modes.
  • tx_sys_reset_out is available in TX/RX_simplex mode.
  • rx_sys_reset_out is available in TX/RX_simplex mode.
reset2fg Output user_clk This port is used to reset the Frame generator in the example design only. This port is available in the TX-only_Simplex and TX/RX_Simplex configurations only.
reset2fc Output user_clk This port is used to reset the Frame checker in the example design only. This port is available in the RX-only_Simplex and TX/RX_Simplex configurations only.
link_reset_out Output init_clk Driven High if hot-plug count expires.
pma_init Input async

The transceiver pma_init reset signal is connected to the top level through a debouncer. Systematically resets all Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) subcomponents of the transceiver. The signal is debounced using init_clk_in for at least six init_clk cycles. See the Reset section in the related transceiver user guide for more details.

GT_SERIAL_RX
rxp[0: m –1](1) Input RX serial clk

Positive differential serial data input pin.

This input is not available in the TX-only_simplex configuration.

rxn[0: m –1](1) Input RX serial clk

Negative differential serial data input pin.

This input is not available in the TX-only_simplex configuration.

GT_SERIAL_TX
txp[0: m –1](1) Output

TX

serial clk

Positive differential serial data output pin.

This output is not available in the RX-only_simplex configuration.

txn[0:m –1](1) Output

TX

serial clk

Negative differential serial data output pin.

This output is not available in the RX-only_simplex configuration.

CORE_STATUS

channel_up/

tx_channel_up/

rx_channel_up

Output user_clk

Asserted when the Aurora 64B/66B channel initialization is complete and the channel is ready to send/receive data.

  • channel_up is available in duplex mode.
  • tx_channel_up is available in TX-only_simplex and TX/RX_simplex mode.
  • rx_channel_up is available in RX-only_simplex and TX/RX_simplex mode.

lane_up[0: m –1]/

tx_lane_up[0: m –1]/

rx_lane_up[0: m –1]

Output user_clk

Asserted for each lane upon successful lane initialization with each bit representing one lane. The Aurora 64B/66B core can only receive data after all lane_up signals are asserted.

  • lane_up is available in duplex mode.
  • tx_lane_up is available in TX-only_simplex and TX/RX_simplex mode.
  • rx_lane_up is available in RX-only_simplex and TX/RX_simplex mode.

soft_err/

tx_soft_err/

rx_soft_err

Output user_clk

Indicates that a soft error is detected in the incoming serial stream (asserted for a single user_clk period).

  • soft_err is available in duplex mode.
  • tx_soft_err is available in TX-only_simplex and TX/RX_simplex mode.
  • rx_soft_err is available in RX-only_simplex and TX/RX_simplex mode.

hard_err/

tx_hard_err/

rx_hard_err

Output user_clk

Hard error detected (asserted until the core resets).

  • hard_err is available in duplex mode.
  • tx_hard_err is available in TX-only_simplex and TX/RX_simplex mode.
  • rx_hard_err is available in RX-only_simplex and TX/RX_simplex mode.
gt_to_common_qpllreset_out Output async Quad phase-locked loop (QPLL) common reset output used by the slave partner shared logic.
gt_pll_lock Output init_clk Asserted when tx_out_clk is stable. When deasserted (Low), circuits using tx_out_clk should be held in reset.
loopback[2:0] Input async See the 7 series FPGAs GTX/GTH Transceivers User Guide (UG476) or UltraScale Architecture GTH Transceivers User Guide (UG576) or UltraScale Architecture GTY Transceivers User Guide (UG578) for details about loopback.
gt_rxcdrovrden_in Input async See the 7 series FPGAs GTX/GTH Transceivers User Guide (UG476) or UltraScale Architecture GTH Transceivers User Guide (UG576) or UltraScale Architecture GTY Transceivers User Guide (UG578) when applicable for details about gt_rxcdrovrden_in.
power_down Input init_clk Drives the Aurora 64B/66B core to reset.
QPLL_CONTROL_IN

gt_qplllock_quad< quad_no >_in, gt_qpllrefclklost_quad< quad_no >_in

(3)
Input init_clk QPLL lock and reference clock lost signal slave partner inputs. Should be connected to the master partner shared logic output ports gt_qplllock_quad< quad_no >_out and gt_qpllrefclklost_quad< quad_no >_out, respectively.
QPLL_CONTROL_OUT

gt_qplllock_quad< quad_no >_out, gt_qpllrefclklost_quad< quad_no >_out

(3)
Output init_clk QPLL lock and reference clock lost signal master partner shared logic outputs.
CHANNEL_DRP_IF(6)(17)(18)
drp_clk_in Input - A user-configurable parameter only applicable to 7 series FPGA designs. The default value is 100 MHz. The drp_clk frequency can be set from 50 MHz to x MHz where x is device and speed grade dependent. In UltraScale devices, init_clk is connected to the DRPCLK port of the GTHE3_, GTHE4_, GTYE3_, GTYE4_CHANNEL DRP interfaces and in the axi_to_drp sub module.

drpaddr_in/

gt< lane >_drpaddr

(8)(14)
Input drp_clk_in DRP address bus. The drpaddress bus is available on a per lane basis.

drpdi_in/

gt< lane >_drpdi

(8)(14)
Input drp_clk_in Data bus for reading configuration data from the transceiver to the FPGA logic resources.The DRP data input bus is available on a per lane basis.

drpen_in_lane_< lane >/

gt< lane >_drpen

(8)(14)
Input drp_clk_in

DRP enable signal.

0 : No read or write operation performed.

1 : Enables a read or write operation.

For write operations, drpwe and drpen should be driven High concurrently for one drp_clk_in cycle only.

For read operations, drpen should be driven High for one drp_clk_in cycle.

The DRP enable is available on a per lane basis.

drpwe_in_lane_< lane >/

gt< lane >_drpwe

(8)(14)
Input drp_clk_in

DRP write enable.

0 : Read operation when drpen is 1.

1 : Write operation when drpen is 1.

For write operations, drpwe and drpen should be driven High for one drpclk cycle only. The DRP write enable is available on a per lane basis.

drpdo_out_lane_<lane >/

gt< lane >_drpdo

(8)(14)
Output drp_clk_in Data bus for reading configuration data from the GTX, GTH, or GTY transceiver to the FPGA logic resources. The DRP data out bus is available on a per lane basis.

drprdy_out_lane_< lane >/

gt< lane >_drprdy

(8)(14)
Output drp_clk_in Indicates that the write operation is complete and read data is valid. The drprdy signal is available on a per lane basis.
AXILITE_DRP_IF(6)
s_axi_awaddr_lane_< lane_no >(2)(9) Input drp_clk_in AXI4-Lite Write address for DRP.
s_axi_awvalid_lane_< lane_no >(2)(9) Input drp_clk_in Write address valid.
s_axi_awready_lane_< lane_no >(2)(9) Output drp_clk_in Write address ready.
s_axi_araddr_lane_< lane_no >(2)(9) Input drp_clk_in AXI4-Lite Read address for DRP.
s_axi_arvalid_lane_< lane_no >(2)(9) Input drp_clk_in Read address valid.
s_axi_arready_lane_< lane_no >(2)(9) Output drp_clk_in Read address ready.
s_axi_wdata_lane_< lane_no >(2)(9) Input drp_clk_in Write data for DRP.
s_axi_wvalid_lane_< lane_no >(2)(9) Input drp_clk_in Write data valid.
s_axi_wready_lane_< lane_no >(2)(9) Output drp_clk_in Write data ready.
s_axi_wstrb_lane_< lane_no >(2)(9) Input drp_clk_in Write data strobe.
s_axi_bvalid_lane_< lane_no >(2)(9) Output drp_clk_in Write response valid.
s_axi_bresp_lane_< lane_no >(2)(9) Output drp_clk_in Write response.
s_axi_rdata_lane_< lane_no >(2)(9) Output drp_clk_in Read data.
s_axi_rvalid_lane_< lane_no >(2)(9) Output drp_clk_in Read data valid.
s_axi_rresp_lane_< lane_no >(2)(9) Output drp_clk_in Read response.
s_axi_rready_lane_< lane_no >(2)(9) Output drp_clk_in Read data ready.
s_axi_bready_lane_< lane_no >(2)(9) Input drp_clk_in Write data ready.
TRANSCEIVER_DEBUG(11)

gt< lane >_cplllock_out/gt_cplllock

(4)(5)(10)(14)
Output init_clk Active-High PLL frequency lock signal indicating that PLL frequency is within the predetermined tolerance. The transceiver and its clock outputs are not reliable until this condition is met.

gt< lane >_dmonitorout_out[ j :0]/gt_dmonitorout

(4)(5)(10)(12)(14)
Output async

Digital Monitor Output Bus.

j = 7 for GTHE2 transceivers.

j = 14 for GTHE2 transceivers.

j= 17 for UltraScale GTH and GTY transceivers

j=16 for UltraScale+ GTH and GTY transceivers

gt< lane >_eyescandataerror_out/gt_eyescandataerror

(4)(5)(10)(12)(14)
Output async Asserted High for one rec_clk cycle when an (unmasked) error occurs while in the COUNT or ARMED state.

gt< lane >_eyescanreset_in/gt_eyescanreset

(4)(5)(10)(12)(14)
Input async Driven High, then deasserted to start the EYESCAN reset process.

gt< lane >_eyescantrigger_in/gt_eyescantrigger

(4)(5)(10)(12)(14)
Input user_clk Causes a trigger event.
gt_pcsrsvdin(4)(10)()(13)(14) Input async PCSRSVDIN[2] is the DRP reset pin. For read-only registers, if a DRPRDY is not seen within 500 DRPCLK cycles after initiating a DRP transaction, reset the DRP interface using the port PCSRSVDIN[2]. This is available only in UltraScale device-based designs.

gt< lane >_rxbufreset_in/gt_rxbufreset

(4)(5)(10)(12)(14)
Input async Driven High, then deasserted to start the RX elastic buffer reset process. In either single or sequential mode, activating rxbufreset resets the RX elastic buffer only.

gt< lane >_rxbufstatus_out/gt_rxbufstatus

(4)(5)(10)(12)(14)
Output rxoutclk

RX buffer status.

000b : Nominal condition.

001b : Number of bytes in the buffer is less than CLK_COR_MIN_LAT.010b : Number of bytes in the buffer is greater than CLK_COR_MAX_LAT.

101b : RX elastic buffer underflow.

110b : RX elastic buffer overflow.

gt<lane >_rxcdrhold_in/gt_rxcdrhold

(4)(5)(10)(12)(14)
Input async Holds the clock data recovery (CDR) control loop frozen.

gt< lane >_rxdfeagchold_in

(5)(10)(12)(13)(14)
Input rxoutclk

HOLD RX DFE (Decision Feedback Equalizer)

2'b00 : Automatic gain control (AGC) loop adapt.

2'b10 : Freeze current AGC adapt value.

2'bx1 : Override AGC value according to the attribute. RX_DFE_GAIN_CFG

gt< lane >_rxdfeagcovrden_in

(5)(10)(12)(13)(14)
Input rxoutclk

OVRDEN RX DFE

2'b00 : Automatic gain control (AGC) loop adapt.

2'b10 : Freeze current AGC adapt value.

2'bx1 : Override AGC value according to attribute.

RX_DFE_GAIN_CFG

gt< lane >_rxdfelfhold_in

(5)(10)(12)(13)(14)
Input rxoutclk When set to 1'b1, the current low-frequency boost value is held. When set to 1'b0, the low-frequency boost is adapted.

gt< lane >_rxdfelpmreset_in/gt_rxdfelpmreset

(4)(5)(10)(12)(14)
Input async Driven High, then deasserted to start the DFE reset process.

gt< lane >_rxlpmen_in/gt_rxplmen

(4)(5)(10)(12)(14)
Input async

RX datapath

0 : DFE

1 : LPM (Low Power Mode)

gt< lane >_rxlpmhfovrden_in

(5)(10)(12)(13)(14)
Input rxoutclk

OVRDEN RX LPM

2'b00 : KH high frequency loop adapt value.

2'b10 : Freeze current adapt value.

2'bx1 : Override KH value according to the RXLPM_HF_CFG attribute.

gt< lane >_rxlpmlfklovrden_in

(5)(10)(12)(13)(14)
Input rxoutclk

OVRDEN RX LPM

2'b00 : KL low frequency loop adapt value.

2'b10 : Freeze current adapt value.

2'bx1 : Override KL value according to the RXLPM_LF_CFG attribute.

gt< lane >_rxmonitorout_out

(5)(10)(12)(13)(14)
Output async

GTX transceiver:

  • RXDFEVP[6:0] = RXMONITOROUT[6:0]
  • RXDFEUT[6:0] = RXMONITOROUT[6:0]
  • RXDFEAGC[4:0] = RXMONITOROUT[4:0]

GTH transceiver:

  • RXDFEVP[6:0] = RXMONITOROUT[6:0]
  • RXDFEUT[6:0] = RXMONITOROUT[6:0]
  • RXDFEAGC[3:0] = RXMONITOROUT[4:1]

gt< lane >_rxmonitorsel_in

(5)(10)(12)(13)(14)
Input async

Select signal for rxmonitorout[6:0]

2'b00 : Reserved.

2'b01 : Select AGC loop.

2'b10 : Select UT loop.

2'b11 : Select VP loop.

gt< lane >_rxpcsreset_in/gt_rxpcsreset

(4)(5)(10)(12)(14)
Input async Driven High, then deasserted to start the RX PMA reset process. The rxpcsreset signal does not start the reset process until rxuserrdy is High.

gt< lane >_rxpmareset_in/gt_rxpmareset

(4)(5)(10)(12)(14)
Input async Driven High, then deasserted to start the RX PMA reset process.

gt< lane >_rxpmaresetdone_out/gt_rxpmaresetdone

(4)(5)(10)(12)(14)
Output async Indicates that the RX PMA reset is complete. Driven Low when GTRXRESET or RXPMARESET is asserted. Available for duplex and RX-only simplex configurations. Available only with GTH transceivers.

gt< lane >_rxprbscntreset_in/gt_rxprbscntreset(4)(5)(10)(12)(14)

Input rxoutclk Resets the PRBS error counter.

gt< lane >_rxprbserr_out/gt_rxprbserr

(4)(5)(10)(12)(14)
Output rxoutclk Non-sticky status output indicates that PRBS errors have occurred.

gt< lane >_rxprbssel_in/gt_rxprbssel(4)(5)(10)(12)(14)

Input rxoutclk

Receiver PRBS checker test pattern control. Valid settings:

000 : Standard operation (PRBS check off).

001 : PRBS-7.

010 : PRBS-15.

011 : PRBS-23.

100 : PRBS-31.

No checking is done for non-PRBS patterns. Single-bit errors cause bursts of PRBS errors because the PRBS checker uses data from the current cycle to generate expected data for the next cycle.

gt_rxrate(4)(10)(12) Input rxoutclk Dynamic pins to automatically change effective PLL dividers in the GTH transceiver RX. These ports are used for PCIe and other standards. Available only with UltraScale and UltraScale+ FPGAs.

gt< lane >_rxresetdone_out/gt_rxresetdone

(4)(5)(10)(12)(14)
Output rxoutclk When asserted, indicates the GTX/GTH/GTY transceiver RX has finished reset and is ready for use. Driven Low when gtrxreset is driven High. Not driven High until rxuserrdy goes High.

gt< lane >_txbufstatus_out/gt_txbufstatus

(4)(5)(10)(11)(14)
Output user_clk

txbufstatus[1] : TX buffer overflow or underflow status. When txbufstatus[1] is set High, the signal remains High until the TX buffer is reset.

1 : TX FIFO has overflow or underflow.

0 : No TX FIFO overflow or underflow error.

txbufstatus[0] : TX buffer fullness.

1 : TX FIFO is at least half full.

0 : TX FIFO is less than half full.

gt< lane >_txdiffctrl_in/gt_txdiffctrl

(4)(5)(10)(11)(14)
Input async Driver Swing Control. Available for duplex and TX-only simplex configurations.

gt<lane>_txinhibit_in/gt_txinhibit

(4)(5)(10)(11)(14)
Input user_clk When High, this signal blocks transmission of TXDATA and forces the serial data output pin TXP to 0 and TXN to 1.
gt< lane >_txmaincursor_in (5)(10)(11)(13)(14) Input async Allows the main cursor coefficients to be set directly if the TX_MAINCURSOR_SEL attribute is set to 1'b1.

gt< lane >_txpcsreset_in/gt_txpcsreset

(4)(5)(10)(11)(14)
Input async Resets the TX PCS. Driven High, then deasserted to start the PCS reset process. Activating this port only resets the TX PCS.

gt< lane >_txpmareset_in/gt_txpmareset

(4)(5)(10)(11)(14)
Input async Resets the TX PMA. Driven High, then deasserted to start the TX PMA reset process. Activating this port resets both the TX PMA and the TX PCS.

gt< lane >_txpolarity_in/gt_txpolarity

(4)(5)(10)(11)(14)
Input user_clk

Inverts the polarity of outgoing data.

0 : Not inverted. TXP is positive, and TXN is negative.

1 : Inverted. TXP is negative, and TXN is positive.

gt< lane >_txpostcursor_in/gt_txpostcursor

(4)(5)(10)(11)(14)
Input async Transmitter post-cursor TX pre-emphasis control.

gt< lane >_txprbsforceerr_in/gt_txprbsforceerr

(4)(5)(10)(11)(14)
Input user_clk When driven High, errors are forced into the PRBS transmitter. While asserted, the output data pattern contains errors. When txprbssel is set to 000, this port does not affect TXDATA.

gt< lane >_txprbssel_in/gt_txprbssel

(4)(5)(10)(11)(14)
Input user_clk

Transmitter PRBS generator test pattern control.

For 7 series devices:

000 : Standard mode (pattern generation off).

001 : PRBS-7.

010 : PRBS-15.

011 : PRBS-23.

100 : PRBS-31.

101 : PCI Express compliance pattern. Only works with 20-bit and 40-bit modes.

110 : Square wave with 2 UI (alternating 0s/1s).

111 : Square wave with 16 UI, 20 UI, 32 UI, or 40 UI period (based on data width).

For UltraScale devices:

4'b0000 : Standard mode (pattern generation off).

4'b0001 : PRBS-7.

4'b0010 : PRBS-9.

4'b0011 : PRBS-15.

4'b0100 : PRBS-23.

4'b0101 : PRBS-31.

4'b1000 : PCI Express compliance pattern. Only works with internal data width 20 bit and 40 bit modes.

4'b1001 : Square wave with 2 UI (alternating 0s/1s).

4'b1010 : Square wave with 16 UI, 20 UI, 32 UI, or 40 UI period (based on internal data width).

gt< lane >_txprecursor_in/gt_txprecusor

(4)(5)(10)(11)(14)
Input async Transmitter pre-cursor TX pre-emphasis control.

gt< lane >_txresetdone_out/gt_txresetdone

(4)(5)(10)(11)(14)
Output user_clk Indicates the GTX/GTH/GTY transceiver TX has finished reset and is ready for use. Driven Low when gttxreset goes High and not driven High until the GTX/GTH/GTY transceiver TX detects txuserrdy High.

gt_qplllock_quad< quad_no >/

gt_qplllock

(3)(4)(5)(10)(11)
Output init_clk Active-High PLL frequency lock signal. Indicates that the PLL frequency is within the predetermined tolerance. The transceiver and its clock outputs are not reliable until this condition is met.
  1. m is the number of GTX, GTH, or GTY transceivers.
  2. lane_no varies from 1 to (number of lanes –1).
  3. In 7 series FPGAs, quad_no varies from 1 to (number of active transceiver quads –1). In UltraScale and UltraScale+ FPGAs, quad_no varies from 1 to the number of active transceiver quads.
  4. Refer to the UltraScale Architecture GTH Transceivers User Guide (UG576) or UltraScale Architecture GTY Transceivers User Guide (UG578) for more information about debug ports.
  5. Refer to the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) for more information about debug ports.
  6. In UltraScale and UltraScale+ devices, all DRP and AXI4-Lite ports are sampled on init_clk.
  7. The Transceiver_Debug ports are enabled if the Additional transceiver control and status ports option is selected in the Debug and Control section of the AMD Vivado™ Integrated Design Environment (IDE) Core Options page. For designs using UltraScale and UltraScale+ devices, the prefixes of the optional transceiver debug ports for single-lane cores are changed from gt< lane > to gt, and the postfixes _in and _out are removed. For multi-lane cores, the prefixes of the optional transceiver debug ports gt(n) are aggregated into a single port.
  8. This port is available if the Native option is selected in the DRP Mode section of the Vivado IDE Core Options page.
  9. This port is available if the AXI4LITE option is selected in the DRP Mode section of the Vivado IDE Core Options page.
  10. This port is available if the Additional transceiver control and status ports option is selected in the DRP Mode section of the Vivado IDE Core Options page.
  11. Available for duplex, TX-Only simplex and TX/RX_simplex configurations.
  12. Available for duplex, RX-Only simplex and TX/RX_simplex configurations.
  13. Not available with UltraScale devices.
  14. lane varies from 0 to (number of lanes –1).
  15. quad varies from 0 to (number of active transceiver quads –1).
  16. Not available in 7 series devices.
  17. Refer to the relevant UG Transceiver guide for more information on DRP ports.
  18. For GT Channel DRP access you can either select the AXI4-Lite interface or the native interface.
  19. GT Common DRP access is not supported.
Important: The ports in the Transceiver Control and Status interface must be driven in accordance with the appropriate GT user guide. Using the input signals listed in Table 1 improperly might result in unpredictable behavior of the IP core.

The following figure shows the status and control interface for an Aurora 64B/66B duplex core.

Figure 1. Aurora 64B/66B Duplex Status and Control Interface

The following figure shows the status and control interface for an Aurora 64B/66B TX-only simplex core.

Figure 2. Aurora 64B/66B TX-Only Simplex Status and Control Interface
Page-1 Rectangle.427 Status and Control Interface Status and Control Interface Standard Arrow.4 Standard Arrow.5 8pt. Arial Text.6 power_down power_down 8pt. Arial Text.7 tx_reset_pb tx_reset_pb Large Arrow.15 Large Arrow.17 Standard Arrow.17 Standard Arrow.19 8pt. Arial Text.12 txp[0:m–1] txp[0:m–1] 8pt. Arial Text.20 txn[0:m–1] txn[0:m–1] 8pt. Arial Text.21 tx_soft_err tx_soft_err 8pt. Arial Text.23 tx_channel_up tx_channel_up Standard Arrow.2 8pt. Arial Text.3 tx_hard_err tx_hard_err Large Arrow.4 8pt. Arial Text.5 tx_lane_up[0:m–1] tx_lane_up[0:m–1]

The following figure shows the status and control interface for an Aurora 64B/66B RX-only simplex core.

Figure 3. Aurora 64B/66B RX-Only Simplex Status and Control Interface
Page-1 Rectangle.427 Status and Control Interface Status and Control Interface Standard Arrow.4 Standard Arrow.5 8pt. Arial Text.6 power_down power_down 8pt. Arial Text.7 rx_reset_pb rx_reset_pb Large Arrow.15 Large Arrow.17 Standard Arrow.17 Standard Arrow.19 8pt. Arial Text.12 rxp[0:m–1] rxp[0:m–1] 8pt. Arial Text.20 rxn[0:m–1] rxn[0:m–1] 8pt. Arial Text.21 rx_soft_err rx_soft_err 8pt. Arial Text.23 rx_channel_up rx_channel_up Standard Arrow.2 8pt. Arial Text.3 rx_hard_err rx_hard_err Large Arrow.4 8pt. Arial Text.5 rx_lane_up[0:m–1] rx_lane_up[0:m–1]

The following figureshows the status and control interface for an Aurora 64B/66B TX/RX Simplex core.

Figure 4. Aurora 64B/66B TX/RX Simplex Status and Control Interface
Page-1 Rectangle.427 Status and Control Interface Status and Control Interface Standard Arrow.4 Standard Arrow.5 8pt. Arial Text.6 power_down power_down 8pt. Arial Text.7 tx_reset_pb tx_reset_pb Large Arrow.15 Large Arrow.17 Standard Arrow.17 Standard Arrow.19 8pt. Arial Text.12 txp[0:m–1] txp[0:m–1] 8pt. Arial Text.20 txn[0:m–1] txn[0:m–1] 8pt. Arial Text.21 tx_soft_err tx_soft_err 8pt. Arial Text.15 tx_channel_up tx_channel_up Standard Arrow.2 8pt. Arial Text.3 tx_hard_err tx_hard_err Large Arrow.4 8pt. Arial Text.5 tx_lane_up[0:m–1] tx_lane_up[0:m–1] Large Arrow.20 Large Arrow.21 8pt. Arial Text.22 rxp[0:m–1] rxp[0:m–1] 8pt. Arial Text.381.23 rxn[0:m–1] rxn[0:m–1] Standard Arrow.24 8pt. Arial Text.25 rx_hard_err rx_hard_err Standard Arrow.26 8pt. Arial Text.27 rx_soft_err rx_soft_err Standard Arrow.28 8pt. Arial Text.29 rx_channel_up rx_channel_up Large Arrow.30 8pt. Arial Text.31 rx_lane_up[0:m–1] rx_lane_up[0:m–1] Standard Arrow.32 8pt. Arial Text.33 rx_reset_pb rx_reset_pb

Loopback support is implemented when the core is generated with the GT outside. The loopback signal can be seen at the top in the example design support.