Shared Logic - 12.0 English

Aurora 64B/66B LogiCORE IP Product Guide (PG074)

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12.0 English

As part of the hierarchical changes to the core, it is now possible to have the core itself include all of the logic which can be shared between multiple cores, which was previously exposed in the example design for the core.

Changes from v11.2 to v12.0:

Added support for Versal devices.

Changes from v11.1 to v11.2:

Aurora IP can now be generated without GT in UltraScale and UltraScale+ based devices.

Changes from v11.0 to v11.1:

Added GTYE4 transceiver support and also added gt_rxusrclk_out transceiver debug output.

Changes from v10.0 to v11.0:

Added GTYE3 transceiver support.

Changes from v9.3 to v10.0:

The following table explains the interfaces and ports updating (addition and removal) in v10.0 of the Aurora 64B/66B core and provides guidance on the impact of these port additions on designs using previous cores.

Table 1. New Ports Added to Aurora 64B/66B in 2015.1
Port Direction Clock Domain Description
reset/ tx_reset/ rx_reset Input user_clk This is used internally in the core.
reset2fg Output user_clk Available in simplex cores. Used to reset the Frame Generator only.
reset2fx Output user_clk Available in simplex cores. Used to reset the Frame Checker only.
gt_pcsrsvdin Input async Optional Transceiver Debug port added.
gt<lane>_txinhibit/ gt_txinhibit Input user_clk Optional Transceiver Debug port added.
do_cc Input user_clk This port is now removed because the standard CC module is part of the core.
  1. Flow control AXI ports are grouped into respective AXI4-Stream interfaces. Control and status ports are grouped into display interfaces.

When IP is upgraded, critical warnings occur due to these port additions. Due to ease-of-use enhancements to the core, the reset/ tx_reset/ rx_reset ports are now connected inside the core. Similarly, the do_cc port is removed because the standard cc module is now part of the core. The removal of these two ports does not interfere with basic functionality.