Revision History - 12.0 English

Aurora 64B/66B LogiCORE IP Product Guide (PG074)
Document ID
PG074
Release Date
2023-11-17
Version
12.0 English
Date Version Revision
11/17/2023 12.0 Added Aurora 64B/66B Characterization appendix.
05/17/2023 12.0
  • Added AM017 reference in the manual.
  • Added Notes in the Throughput section
  • Added a note in Table Aurora 64B/66B Core Clock Ports
  • Added UG901 reference in the References.
10/19/2022 12.0
  • Updated GUI Options Tab for Versal Device section with additional line rate information.
  • Extended Versal GTM and GTYP support from 8 lanes to 16.
04/27/2022 12.0
  • Updated GUI Options Tab for Versal Device section with GT Type information.
  • Updated figures in Status Control and Transceiver Ports
12/04/2020 12.0
  • Added support for Versal Adaptive SoC.
  • Updated Device Migration section.
05/15/2019 12.0 Updated the core to v12.0.
04/04/2018 11.2 Added framing mode packet format for > 16.375 Gbps.
10/04/2017 11.2 Updated references for throughput section.
04/05/2017 11.2 Added support to generate Aurora without GT for UltraScale and UltraScale+ devices.
10/05/2016 11.1 Removed the Example design directory structure due to the updates in Vivado flows for 2016.3.
06/08/2016 11.1
  • Added Reference to GT_Debug_Flowchart in AR 57237
  • Updated C_EXAMPLE_SIMULATION usage description
  • Updated Unsupported features
  • Updated references to UG578
04/06/2016 11.1 Added Managed Shared Logic Files section under Output Generation in Chapter 4: Design Flow Steps.
11/18/2015 11.0 Added support for UltraScale+ families.
12/14/2015 11.0 Added UltraScale+ families to the IP Facts table
09/30/2015 11.0
  • Updated first paragraph in Port Descriptions section.
  • Added bufg_gt_clr_out and a note to Table 2-6.
  • Added a note (19) to Table 2-11.
  • Added GTY transceiver support.
  • Updated graphics in Chapter 4, Design Flow Steps.
04/01/2015 10.0
  • General changes
  • Updated Max line rate information.
  • Updated information for GT location selection option for UltraScale devices
  • Grouped Flow control AXI ports into AXI4-Stream interface.
  • Added as a single row entry the interface to which a port belongs.
  • Updated single ended clock option information.
  • Added support for the Simplex Auto Link Recovery feature
  • Updated Reset section.
  • Moved all of the material in the Core Features chapter to the end of Chapter 3, Designing with the Core. Deleted Chapter 4.
  • Added Single/Differential clocking option for GTREFCLK and core INIT_CLK
  • Removed data strobe information
  • Removed do_cc information.
  • Chapter 2, Product Specification
  • Updated TX user interface description
  • Updated Figure 2-4, Figure 2-12, Figure 22-14.
  • Added reset2fg, reset2fc, gt_pcsrsvdin, gt<lane>_txinhibit_in/gt_txinhibit to Table 2-13: Transceiver Control and Status Interface Ports table.
  • Added the CORE_STATUS, GT_SERIAL_RX, GT_SERIAL_TX, CORE_CONTROL, QPLL_CONTROL_OUT, and QPLL_CONTROL_IN headings to Table 2-13.
  • Removed reset/tx_reset/rx_reset from Table 2-14.
  • Added Checking CRC at Core Level subsection to CRC Interface section.
  • Chapter 3, Designing with the Core
  • Moved all of the material from the Core Features chapter to this chapter. Removed the Core Features chapter.
  • Added a note to Figure 3-1. Updated Figure 3-2, Figure, 3-3, Figure 3-6, Figure 3-17.
04/01/2015 10.0
  • Revised the following sections: Reset Sequencing, Aurora 64B/66B Simplex Power On Sequence, Aurora 64B/66B Simplex Normal Operation Reset Sequence, Aurora 64B/66B Simplex TX and RX, and Reset Flow.
  • Added a Single Ended option note to the Shared Logic section.
  • Revised Clock Compensation section and moved to this chapter.
  • Updated Figure 3-6, Figure 4-3, Figure 5-1, Figure B-3.
  • Chapter 4, Design Flow Steps (previously, Chapter 5)
  • Updated all screen captures.
  • Added four options to the Core Options tab: Lanes, Starting GT Quad, Starting GT Lane, and GT Refclk Selection.
  • Added two parameters to Table 4-1: Single Ended INIT CLK and Single Ended GTREF CLK
  • Removed Transceiver Channel Locations section.
  • Deleted Figure 4-4
  • Replaced code in Example Design section.
  • Added six rows to User Parameters table: Column Used, Starting GT Quad, Starting GT Lane, GT Refclk Selection, Single Ended INIT CLK, and Single Ended GTREF CLK.
  • Added notes 11 and 12 to Table 4-1.
  • Removed Transceiver Channel Locations section.
  • Deleted Figure 4-4 and the text following the figure.
  • Appendix A: Verification, Compliance, and Interoperability
  • Added Table A-3: 2015.1 Aurora 64B/66B Interoperability.
  • Updated the release numbers in the bulleted items under BACKWARD_COMP_MODE1 /BACKWARD_COMP_MODE2 and BACKWARD_COMP_MODE3
  • Appendix B: Migrating and Upgrading
  • Removed existing rows from Table B-1 and added six new rows.
  • Modified Overview of Major Changes section.
  • Updated Figure B-3.
  • Appendix C: Debugging
  • Changed “Vivado lab tools” to “Vivado Lab Edition.”
10/01/2014 9.3
  • Added new v9.3 core features and attributes.
  • Rearranged content to consolidate topics and better conform to template
06/04/2014 9.2 Added User Parameter information.
04/02/2014 9.2
  • Added C_EXAMPLE_SIMULATION parameter for post synthesis/implementation simulation speedup.
  • Added support for UltraScale devices.
  • Enhanced support for IP integrator
  • Added Little endian support for data and flow control interfaces as non-default Vivado IDE selectable option.
  • Provided interoperability guidance.
  • Resolved functional issue seen with specific frame lengths in certain scenarios.
12/18/2013 9.1
  • Added default information to init_clk_p, initclk_n, and INIT_CLK description.
  • Updated reset sequencing steps and waveform.
  • Added information about pma_init staging.
  • Updated screen captures.
  • Added sequence of steps describing hardware FSM reset
10/02/2013 9.0
  • Added new chapters: Simulation, Test Bench and Synthesis and Implementation.
  • Added shared logic and transceiver debug features.
  • Updated directory and file structure.
  • Changed signal and port names to lowercase.
  • Added Zynq 7000 device support
  • Updated RX datapath architecture
  • Updated Aurora Simplex Operation description.
  • Updated Figure 3-2 and screen captures in Chapter 4.
  • Updated Hot-Plug Logic description.
  • Added IP integrator support.
  • Updated XDC file for the example design.
  • Added design bring-up on evaluation board information.
06/19/2013 8.1
  • Revision number advanced to 8.1 to align with core version number.
  • Updated for 2013.2 release and core version 8.1.
  • Fixed a NFC transmit failure scenario when Clock Correction is transmitted in conjunction with the second NFC request. NFC state machine is updated to handle such scenarios.
03/20/2013 2.0
  • Updated for 2013.1 release and core version 8.0.
  • Removed all ISE design tools and Virtex-6 related device information.
  • Added Reset waveforms
  • Updated debug guide with core and transceiver debug details
  • Created lowercase ports for Verilog
  • Added Simplex TX/RX support
  • Enhanced protocol to increase Channel Init time
  • Included TXSTARTUPFSM and RXSTARTUPFSM modules to control GT reset sequence
12/18/2012 1.0.1
  • Updated for 14.4 and 2012.4 release.
  • Added TKEEP description
  • Updated Debugging appendix.
10/16/2012 1.0
  • Initial Xilinx release as a product guide. This document replaces UG775, LogiCORE IP Aurora 64B/66B User Guide and DS815, LogiCORE IP Aurora 64B/66B Data Sheet .
  • Added section explaining constraining of the core.
  • Added section explaining core debugging.