The top-level RESET input (example design level) is debounced and connected to
the core (reset_pb). This signal is aggregated with the
serial transceiver reset status and the hot-plug reset from within the core reset logic
(sys_reset_out) to generate a reset to the core.
This signal is expected to connect to the core reset input. The following figure
illustrates this behavior.
Figure 1. Reset Flow
