Because the core has no built-in buffer for user data, there is no
m_axi_rx_tready
signal on the RX AXI4-Stream interface. User application control of the
flow of data from an Aurora 64B/66B channel is limited to one of the optional core flow
control features.
The m_axi_rx_tvalid
signal is asserted concurrently with the first word of
each frame from the core. The m_axi_rx_tlast
signal is
asserted concurrently with the last word or partial word of each frame. The m_axi_rx_tkeep
port indicates the number of valid bytes in
the final word of each frame using the same byte indication procedure as s_axi_tx_tkeep
. All bytes valid are indicated (all 1s)
when m_axi_rx_tlast
is not asserted and the exact
number of bytes valid is specified when m_axi_rx_tlast
is asserted.
If the CRC option is selected, the received
data stream is computed for the expected CRC value. The CRC block re-calculates the
m_axi_rx_tkeep
value and correspondingly asserts
m_axi_rx_tlast
.
The core can deassert m_axi_rx_tvalid
anytime, even during a frame.