Product Specification - 12.0 English

Aurora 64B/66B LogiCORE IP Product Guide (PG074)

Document ID
PG074
Release Date
2023-11-17
Version
12.0 English

The functional block diagram of the core is shown in the following figure.

Figure 1. Aurora 64B/66B Core Block Diagram
The major functional modules of the Aurora 64B/66B core are:
Lane logic
An instance of the lane logic module drives each GT transceiver. This lane logic initializes each individual transceiver, handles the encoding and decoding of control characters, and performs error detection.
Global logic
The global logic module in the core performs the channel bonding for channel initialization. During operation, the channel keeps track of the Not Ready idle characters defined by the Aurora 64B/66B protocol and monitors all the lane logic modules for errors.
RX user interface
The AXI4-Stream receive (RX) user interface moves data from the channel to the application and also performs flow control functions.
TX user interface
The AXI4-Stream transmit (TX) user interface moves data from the application to the channel and also performs flow control TX functions. The standard clock compensation module is embedded inside the core. This module controls the periodic transmission of the clock compensation (CC) character.