When power_down is asserted, only the Aurora 64B/66B core logic is
reset. This does not turn off the GTX, GTH, or GTY transceivers used in the design.
CAUTION:
Be careful when asserting this signal on
cores that use
tx_out_clk (see Reference Clocks for FPGA Designs). tx_out_clk stops when
the GTX, GTH, and GTY transceivers are powered down. See the
7
Series FPGAs GTX/GTH Transceivers User Guide (UG476),
UltraScale
Architecture GTH Transceivers User Guide (UG576),
UltraScale Architecture GTY Transceivers User Guide
(UG578),
Versal
Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002), and
Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017) for power saving
details.