The major change to the core is the addition of the AXI4-Stream interface:
- Max line rate support of 16.375G added for UltraScale GTHE3/GTHE4 transceivers.
- Extended the Max line rate support of up to 25.7813G for GTYE3/GTYE4 transceivers.
- Line rate value restricted to four decimal digits for UltraScale and UltraScale+ devices with the exception of 25.78125 Gbps for GTY devices.
- GT location selection option for UltraScale device added to the core.
- Added support for simplex auto recovery.
- Flow control ports are grouped into AXI4-Stream interfaces.
- Control and Status ports are grouped into display interfaces.
- Single-ended clock option added to the core for
init_clk
andgt_refclk
. - Both reset inputs
pma_init
andreset_pb
made asynchronous. The reset,tx_reset
, andrx_reset
input ports were removed. - CRC resource utilization optimized.
- Standard CC module made part of the IP. The do_cc port was removed.
- INIT clock frequency value can take up to six decimal digits.