Latency - 12.0 English

For a default single lane configuration, latency through an Aurora 64B/66B core is caused by pipeline delays through the protocol engine (PE), GTX, and GTH transceivers. The PE pipeline delay increases as the AXI4-Stream interface width increases. The transceiver delays are determined by the transceiver features.

This section outlines a method of measuring the latency for the Aurora 64B/66B core AXI4-Stream user interface in terms of user_clk cycles for AMD Zynq™ 7000, AMD Virtex™ 7, AMD Kintex™ 7 (GTX and GTH transceiver-based designs), AMD UltraScale™ , and AMD UltraScale+™ devices (GTH and GTY transceiver-based designs). For the purposes of illustrating latency, the Aurora 64B/66B modules are partitioned between logic in the GTX, GTH, GTY transceivers, and protocol engine (PE) logic implemented in the FPGA.

The following figure illustrated the latency of the data path.

Figure 1. Latency of the Datapath

The latency must be measured from the rising edge of the transmitter user_clk at the first assertion of s_axi_tx_tvalid and s_axi_tx_tready to the rising edge of the receiver user_clk at the first assertion of m_axi_rx_tvalid. The following figure shows the transmitter and receiver path reference points between which the latency has been measured for the default core configuration.

Figure 2. Latency Waveform with Reference Points

The following table shows the maximum latency and the individual latency values of the contributing pipeline components for the default core configuration on 7 series GTX/GTH and UltraScale/UltraScale+ GTH transceiver-based devices. Latency can vary with the addition of flow controls.

The pipeline delays are designed to maintain the clock speed.