See the diagram in the information area in Figure 1. Each numbered row represents a serial transceiver tile and each active box represents an available GTX or GTH transceiver. For each Aurora 64B/66B lane in the core, starting with Lane 1, select a GTX or GTH transceiver and place the lane by selecting its number in the GTX or GTH transceiver placement box.
- X in the drop-down menu means that lane is not selected.
- <1—16> selected from the drop-down menu means that particular lane is selected. It does not assign that number to the physical lane.
Recommended: Always select consecutive/physically adjacent
lanes for a multi-GT design.
Note: The core generates transceiver placement (LOC) constraints in
ascending fashion. Move the cursor in the Vivado IDE to see the
transceiver being selected in the 7 series and
Zynq 7000 family-based design. Lane
numbering serves only to enable the lanes and not to assign numbers to the lanes. The
Lane Assignment is not available for UltraScale architecture-based
designs. It is strongly recommended that the lane selection should be continuous for
timing closure.