Generation of Aurora without GT

Generation of Aurora without GT - 12.0 English

Aurora 64B/66B LogiCORE IP Product Guide (PG074)

Document ID

PG074

Release Date

2023-11-17

Version

12.0 English

This option is available only in UltraScale and UltraScale+ devices. When enabled, it generates the Aurora core without the GT and moves the transceiver from the core to the support level in example design. The following table provides the list of ports used to interact with the GT transceiver, outside the Aurora IP.

Table 1. List of Ports Used to Interact with GT Transceiver
Name	Direction	Clock Domain	Description
rxusrclk_in	Input	-
gt<i>_txoutclk_in⁽²⁾	Input	-	Connects to TXOUTCLK on transceiver channel primitives.⁽³⁾
gttx_fsm_resetdone_in	Input	user_clk	Active-High indication to Aurora that the transmitter reset sequence of transceiver primitives as initiated by the reset controller helper block has been completed.
gtrx_fsm_resetdone_in	Input	rxusrclk_in	Active-High indication to Aurora that the receiver reset sequence of transceiver primitives as initiated by the reset controller helper block has been completed.
fabric_pcs_reset_in	Input	user_clk	Active-High indication to Aurora that the fabric logic must be kept in reset.
userclk_rx_active_in	Input	rxusrclk_in
rxdata_lane<i>_in⁽¹⁾	Input	rxusrclk_in	Data beats received from the GT.
rxheader_lane<i>_in⁽¹⁾	Input	rxusrclk_in	Indicates whether data or control beat is received.
rxdatavalid_lane<i>_in⁽¹⁾	Input	rxusrclk_in	Status output from GT which indicates data received on RXDATA bus is valid.
rxheadervalid_lane<i>_in⁽¹⁾	Input	rxusrclk_in	Indicates that the RXHEADER is valid when using the gearbox.
rxfsm_reset_out	Output	init_clk	Active-High sent to reset GT RX datapath.
rxpolarity_out	Output	user_clk	Active-High if Aurora detects polarity reversal in incoming rxdata.
rxgearboxslip_lane<i>_out⁽¹⁾	Output	rxusrclk_in	When High, this port causes the gearbox contents to slip to the next possible alignment. This port is used to achieve alignment with the interconnect logic. Asserting this port for one RXUSRCLK2 cycle changes the data alignment coming out of the gearbox.⁽³⁾
txheader_lane<i>_out⁽¹⁾	Output	user_clk	Indicates whether data or control beat is transmitted to GT.
txuserdata_lane<i>_out⁽¹⁾	Output	user_clk	Connected to the user interface in UltraScale+ GT Wizard for data to be transmitted by transceiver channels.
txsequence_lane<i>_out ⁽⁴⁾	Output	user_clk	This port is used by UltraScale+ GT Wizard for the interconnect logic sequence counter when the TX gearbox is used.
lane<i> is added for a multilane design where i = 1 to N-1 where N is the number of lanes chosen. i= 1 to N, where N is the number of lanes chosen. Refer to the UltraScale Architecture GTH Transceivers User Guide (UG576) or UltraScale Architecture GTY Transceivers User Guide (UG578), when applicable. lane<i> is available with a similar connotation as Note 1, but only for GTY based configurations. Do not try to reconfigure a GT that is not generated by this IP core.