The transceiver attributes play a vital role in the functionality of the AMD LogiCORE™ IP Aurora 64B/66B core. Use the latest transceiver wizard to generate the transceiver wrapper file.
Important:
AMD strongly recommends updating
the transceiver wrapper file in the AMD Vivado™
Design Suite tool releases
when the transceiver wizard has been updated but the Aurora 64B/66B core has not.
Use these steps to generate the transceiver wrapper file using the 7 series FPGAs Transceivers Wizard:
- Using the Vivado IP catalog, run the latest version of the 7 series FPGAs Transceivers Wizard. Ensure the Component Name of the transceiver wizard matches the Component Name of the Aurora 64B/66B core.
- Select the protocol template: Aurora 64B/66B.
- Set the Line Rate for both the TX and RX transceivers based on the application requirement.
- Select the Reference Clock from the drop-down menu for both the TX and RX transceivers based on the application requirement.
- Select transceiver(s) and the clock source(s) based on the application requirement.
- On Page 3, select External Data Width of the RX transceiver to be 32 Bits and Internal Data Width to be 32 bits. Ensure that the TX transceiver is configured with 64-bit external data width and 32-bit internal data width.
- Keep all other settings as default.
- Generate the core.
- Replace the
<user_component_name>_gtx.v
file in theexample_design/gt/ directory
available in the Aurora 64B/66B core with the generated<user_component_name>_gt.v
file generated from the 7 series FPGAs Transceivers Wizard.The transceiver settings for the Aurora 64B/66B core are now up to date.
Note: The UltraScale architecture Aurora 64B/66B core
uses the hierarchical core calling method to call the UltraScale device
GTWizard IP core. In this way, all the transceiver attributes, parameters, and required
workarounds are up to date. Manual editing of the UltraScale device
transceiver files are not required in most cases.