GT DRP clk (MHz) - 13.0 English - PG074

Aurora 64B/66B LogiCORE IP Product Guide (PG074)

Document ID
PG074
Release Date
2024-12-11
Version
13.0 English

Enter a valid DRP clock frequency in the text box. Available only with 7 series FPGA transceivers.

Default: 100 MHz