Framing Efficiency - 13.0 English - PG074

There are two factors that affect framing efficiency in the Aurora 64B/66B core:

1. The size of the frame
2. A data invalid request from the gearbox occurs after every 32 user_clk(txusrclk2) cycles

The gearbox in GTX and GTH transceivers requires a periodic pause to account for the clock divider ratio and 64B/66B encoding. This appears as back pressure in the AXI4-Stream interface and the user data needs to be stopped for one cycle after every 32 cycles (as shown in the following figure). The s_axi_tx_tready signal in the user interface from the Aurora 64B/66B core is deasserted for one cycle, once after every 32 cycles. The pause cycle is used to compensate the gearbox for the 64B/66B encoding.

For more information on gearbox pause in GTX/GTH/GTY transceivers, see the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) or the UltraScale Architecture GTH Transceivers User Guide (UG576), or the UltraScale Architecture GTY Transceivers User Guide (UG578), when applicable.

The Aurora 64B/66B core implements the Strict Aligned option of the Aurora 64B/66B protocol. No data blocks are placed after idle blocks or SEP blocks on a given cycle. The following table is an example calculated after including overhead for clock compensation (CC sequence consisting of a maximum of eight CC characters is sent every 4,992 user_clk cycles) and shows the efficiency for a single-lane channel while illustrating that the efficiency increases as frame length increases.

The following table shows the overhead in a single-lane channel when transmitting 256 bytes of frame data. The resulting data unit is 264 bytes long due to the end-of-frame SEP block. This results in a 3.03% transmitter overhead. Also, the clock compensation blocks must be transmitted for at least three cycles every 10,000 cycles resulting in an additional 0.03% overhead in the transmitter.