The generated example design including support logic has a 3.125 Gbps line rate and a 156.25 MHz reference clock. The XDC file generated for xc7vx485tffg1157-1, the default device, follows:
################################ CLOCK CONSTRAINTS #########################
#User Clock Constraint: the value is selected based on the line rate of the module
#create_clock -period 20.48 [get_pins aurora_64b66b_0_block_i/clock_module_i/user_clk_net_i/I]
# SYNC Clock Constraint
#create_clock -period 10.240 [get_pins aurora_64b66b_0_block_i/clock_module_i/sync_clock_net_i/I]
################################ IP LEVEL CONSTRAINTS START ################
# Following constraints present in aurora_64b66b_0.xdc
# Create clock constraint for TXOUTCLK from GT
#create_clock -period 10.240 [get_pins -hier -filter {name=~*aurora_64b66b_0_wrapper_i*aurora_64b66b_0_multi_gt_i*aurora_64b66b_0_gtx_inst/gtxe2_i/TXOUTCLK}]
# Create clock constraint for RXOUTCLK from GT
#create_clock -period 10.240 [get_pins -hier -filter {name=~*aurora_64b66b_0_wrapper_i*aurora_64b66b_0_multi_gt_i*aurora_64b66b_0_gtx_inst/gtxe2_i/RXOUTCLK}]
################################ IP LEVEL CONSTRAINTS END ##################
# Reference clock constraint for GTX
create_clock -period 6.400 [get_ports GTXQ1_P]
### DRP Clock Constraint
create_clock -period 10.000 [get_ports DRP_CLK_IN]
# 50MHz board Clock Constraint
create_clock -period 20.000 [get_ports INIT_CLK_P]
###### No cross clock domain analysis. Domains are not related ##############
## set_false_path -from [get_clocks init_clk] -to [get_clocks user_clk]
## set_false_path -from [get_clocks user_clk] -to [get_clocks init_clk]
## set_false_path -from [get_clocks init_clk] -to [get_clocks sync_clk]
## set_false_path -from [get_clocks sync_clk] -to [get_clocks init_clk]
## ## set_false_path -from init_clk -to [get_clocks -of_objects [get_pins aurora_64b66b_0_block_i/clock_module_i/mmcm_adv_inst/CLKOUT0]]
##
## ## set_false_path -from [get_clocks -of_objects [get_pins aurora_64b66b_0_block_i/clock_module_i/mmcm_adv_inst/CLKOUT0]] -to init_clk
##
## ## set_false_path -from init_clk -to [get_clocks -of_objects [get_pins aurora_64b66b_0_block_i/clock_module_i/mmcm_adv_inst/CLKOUT1]]
##
## ## set_false_path -from [get_clocks -of_objects [get_pins aurora_64b66b_0_block_i/clock_module_i/mmcm_adv_inst/CLKOUT1]] -to init_clk
##
## ## set_false_path -from [get_clocks -of_objects [get_pins aurora_64b66b_0_block_i/clock_module_i/initclk_bufg_i/O]] -to [get_clocks -of_objects [get_pins -hier -filter {name=~*aurora_64b66b_0_i*inst*aurora_64b66b_0_wrapper_i*aurora_64b66b_0_multi_gt_i*aurora_64b66b_0_gtx_inst/gtxe2_i/RXOUTCLK}]]
##
## ## set_false_path -from [get_clocks -of_objects [get_pins -hier -filter {name=~*aurora_64b66b_0_i*inst*aurora_64b66b_0_wrapper_i*aurora_64b66b_0_multi_gt_i*aurora_64b66b_0_gtx_inst/gtxe2_i/RXOUTCLK}]] -to [get_clocks -of_objects [get_pins aurora_64b66b_0_block_i/clock_module_i/initclk_bufg_i/O]]
##
## ## set_false_path -from [get_clocks -of_objects [get_pins -hier -filter {name=~*aurora_64b66b_0_i*inst*aurora_64b66b_0_wrapper_i*aurora_64b66b_0_multi_gt_i*aurora_64b66b_0_gtx_inst/gtxe2_i/RXOUTCLK}]] -to [get_clocks -of_objects [get_pins aurora_64b66b_0_block_i/clock_module_i/mmcm_adv_inst/CLKOUT0]]
##
## ## set_false_path -from [get_clocks -of_objects [get_pins aurora_64b66b_0_block_i/clock_module_i/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins -hier -filter {name=~*aurora_64b66b_0_i*inst*aurora_64b66b_0_wrapper_i*aurora_64b66b_0_multi_gt_i*aurora_64b66b_0_gtx_inst/gtxe2_i/RXOUTCLK}]]
## GT CLOCK Locations ##
# Differential SMA Clock Connection
set_property LOC AH6 [get_ports GTXQ1_P]
set_property LOC AH5 [get_ports GTXQ1_N]
set_property LOC GTXE2_CHANNEL_X1Y4 [get_cells aurora_64b66b_0_block_i/aurora_64b66b_0_i/inst/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/gtxe2_i]
# false path constraints to the example design logic
set_false_path -to [get_pins -hier *aurora_64b66b_0_cdc_to*/D]
#####################################################################################################
##Note: User should add LOC based upon the board
# Below LOC's are place holders and need to be changed as per the device and board
#set_property LOC D17 [get_ports INIT_CLK_P]
#set_property LOC D18 [get_ports INIT_CLK_N]
#set_property LOC G19 [get_ports RESET]
#set_property LOC K18 [get_ports PMA_INIT]
#set_property LOC A20 [get_ports CHANNEL_UP]
#set_property LOC A17 [get_ports LANE_UP]
#set_property LOC Y15 [get_ports HARD_ERR]
#set_property LOC AH10 [get_ports SOFT_ERR]
#set_property LOC AD16 [get_ports DATA_ERR_COUNT[0]]
#set_property LOC Y19 [get_ports DATA_ERR_COUNT[1]]
#set_property LOC Y18 [get_ports DATA_ERR_COUNT[2]]
#set_property LOC AA18 [get_ports DATA_ERR_COUNT[3]]
#set_property LOC AB18 [get_ports DATA_ERR_COUNT[4]]
#set_property LOC AB19 [get_ports DATA_ERR_COUNT[5]]
#set_property LOC AC19 [get_ports DATA_ERR_COUNT[6]]
#set_property LOC AB17 [get_ports DATA_ERR_COUNT[7]]
#set_property LOC AG29 [get_ports DRP_CLK_IN]
#// DRP CLK needs a clock LOC
##Note: User should add IOSTANDARD based upon the board
# Below IOSTANDARDs are place holders and need to be changed as per the device and board
#set_property IOSTANDARD DIFF_HSTL_II_18 [get_ports INIT_CLK_P]
#set_property IOSTANDARD DIFF_HSTL_II_18 [get_ports INIT_CLK_N]
#set_property IOSTANDARD LVCMOS18 [get_ports RESET]
#set_property IOSTADARD LVCMOS18 [get_ports PMA_INIT]
#set_property IOSTANDARD LVCMOS18 [get_ports CHANNEL_UP]
#set_property IOSTANDARD LVCMOS18 [get_ports LANE_UP]
#set_property IOSTANDARD LVCMOS18 [get_ports HARD_ERR]
#set_property IOSTANDARD LVCMOS18 [get_ports SOFT_ERR]
#set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[0]]
#set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[1]]
#set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[2]]
#set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[3]]
#set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[4]]
#set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[5]]
#set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[6]]
#set_property IOSTANDARD LVCMOS18 [get_ports DATA_ERR_COUNT[7]]
#set_property IOSTANDARD LVCMOS18 [get_ports DRP_CLK_IN]
#// DRP CLK needs a clock IOSTDLOCThe preceding example XDC is for reference only. This XDC is created automatically when the core is generated from the AMD Vivado™ design tools.