The following figure shows an example of a simple n byte wide data
transfer. 3 n bytes of data are sent requiring three data beats. s_axi_tx_tready is asserted indicating that the AXI4-Stream interface is ready to transmit data.
To begin the data transfer, the user application asserts s_axi_tx_tvalid and provides the first n bytes of the user
frame. Because s_axi_tx_tready is already asserted,
the data transfer begins on the next clock edge. The data bytes are placed in data
blocks and transferred through the Aurora 64B/66B channel.
To end the data transfer, the user application
asserts s_axi_tx_tlast, s_axi_tx_tvalid, the last data bytes, and the appropriate TKEEP value (0xFF) on
the s_axi_tx_tkeep bus. The core sends the final data
word in blocks and must send an empty separator block on the next cycle to indicate the
end of the frame. s_axi_tx_tready is reasserted on the
next cycle so that more data transfers can continue. If there is no new data, the Aurora
64B/66B core sends idles.