If migrating from a 7 series device with GTX or GTH transceivers to an AMD UltraScale™
device with GTH transceivers, the
prefixes of the optional transceiver debug ports for single-lane cores are changed
from “gt0”, “gt1” to
“gt”, and the suffix “_in” and “_out” are dropped. For
multi-lane cores, the prefixes of the optional transceiver debug ports gt(n) are
aggregated into a single port. For example: gt0_gtrxreset and gt1_gtrxreset now
become gt_gtrxreset
[1:0]. This is true for all ports, with the
exception of the DRP buses, which follow the convention of gt(n)_drpxyz.
Note: It is important that designs are updated to use the
new transceiver debug port names. For more information about migration to UltraScale devices, see the
UltraScale Architecture Migration: Methodology Guide
(UG1026).
Perform any one of the following steps when migrating to an AMD Versal™ Adaptive SoC:
- Instantiate Aurora IP in the IP integrator. For more information, see Xilinx IP - GT Wizard Integration.
- Generate Aurora IP from the Vivado IP
catalog, open example design. Versal adaptive SoC
Aurora IP example design has an IP integrator based reference design as shown in
Figure 1. Refer the
example design wrapper file
<IP_inst_name>_exdes_bd_wrapperas shown in Figure 2. This wrapper file has the necessary connections between Aurora and gt_quadbase IP. For more information, see Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331)
Figure 1. Aurora Example Design
Figure 2. Aurora Example Design BD Wrapper
