The DRP interface allows user applications to monitor and modify the transceiver status. The native interface provides the native transceiver DRP interface ports. The AXI4-Lite interface (fully compliant with the AXI4-Lite protocol) is the default interface.
For native DRP sequences, the read and write
operations are as specified in the respective FPGA Transceivers User Guides. For AXI4-Lite DRP sequences, the read and write operations
from the user interface are specified in the AXI4-Lite
protocol. The Aurora 64B/66B core does not use the wstrb signal (refer to the
Vivado Design Suite: AXI Reference
Guide (UG1037). The axi_to_drp module is used
to translate between the transceiver DRP and AXI4-Lite
protocols.