This section includes information about using AMD tools to customize and generate the core in the AMD Vivado™ Design Suite.
If you are customizing and generating
the core in the
Vivado IP integrator, see
the
Vivado Design Suite User Guide: Designing
IP Subsystems using IP Integrator (UG994) for
detailed information. IP integrator might auto-compute certain
configuration values when validating or generating the design. To
check whether the values do change, see the description of the
parameter in this chapter. To view the parameter value, run the
validate_bd_design command in the Tcl
console.
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
- Select the IP from the IP catalog.
- Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).
Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.
The Aurora 64B/66B core can be customized to suit a wide variety of requirements using the IP catalog. This chapter details the customization parameters and how these parameters are specified within the Vivado Integrated Design Environment (IDE).
Figure 1 through Figure 1 show the features described in the corresponding sections. The left side displays a representative block diagram of the Aurora 64B/66B core as currently configured. The right side consists of user-configurable parameters.
Figure 1 shows the Core Options tab of the Customize IP interface with the default options for Zynq 7000 and 7 series devices.