During power-on for both TX simplex and RX simplex cores, the pma_init
and reset_pb signals are expected to be High. INIT_CLK
and GT_REFCLK are expected to be stable during the power-on sequence.
Due to the auto simplex recovery feature, both boards can be brought up independently.
If the RX board is brought up first, then when the TX board is brought up, data
transmission can start immediately. However, if the TX board is brought up first, then
no data transmission should take place until the RX board comes up based on the periodic
CB pattern sent by TX.
Aurora 64B/66B Simplex Power On Sequence
Aurora 64B/66B Simplex Normal Operation Reset Sequence
For simplex configurations, because the TX and RX can be powered on
independently, data transmission must begin only after rx_channel_up is seen (that is, after a minimum of 45 ms of tx_channel_up), to avoid loss of data. Before asserting
pma_init, the reset_pb must be asserted for a
minimum time equal to 128*user_clk time period to
ensure that the portion of the core in programmable logic goes to a known reset
state before the user_clk is held Low during the
pma_init assertion. The assertion time of the
pma_init must be a minimum of six INIT_CLK cycle time period to satisfy the requirements
of the core debouncing circuit.
