Aurora 64B/66B Frames - 12.0 English

Aurora 64B/66B LogiCORE IP Product Guide (PG074)

Document ID
PG074
Release Date
2023-11-17
Version
12.0 English

All Aurora 64B/66B data is sent as part of a data block or a separator block. A separator block (SEP) consists of a count field indicating how many bytes are valid in that particular block. In framing, each frame begins with data blocks and ends with a separator block containing the last bytes of the frame. Idle blocks are inserted whenever data is not available. Blocks are eight bytes of scrambled data or control information with a two-bit control header (a total of 66 bits).

The following table shows a typical Aurora 64B/66B frame with an even number of data bytes.

Table 1. Typical Channel Frame
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 . . . Data Byte n –2 Data Byte n –1 Data Byte n
SEP (1E) Count (4) Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 x x

To transmit the data, the user application configures the control signals causing the core to perform these steps:

  1. Accept data from the user application on the s_axi_tx_tdata bus.
  2. Indicate the end of the frame when s_axi_tx_tlast is asserted along with s_axi_tx_tkeep and stripe data across lanes in the Aurora 64B/66B channel.
  3. Assembles data for presentation to the user application on the m_axi_rx_tdata bus including providing the number of valid bytes on m_axi_rx_tkeep and asserts m_axi_rx_tvalid during the m_axi_rx_tlast cycle.

When the core receives data, it performs these steps:

  1. Detects and discards control bytes (idles, clock compensation).
  2. Recovers data from the lanes.
  3. Assembles data for presentation to the user application on the m_axi_rx_tdata bus including providing the number of valid bytes on m_axi_rx_tkeep and asserts m_axi_rx_tvalid during the m_axi_rx_tlast cycle.

Data striping is handled differently for line-rates above 16.375 Gbps. See the following table for this packet format. Specifically, on the last cycle of a frame, all the lanes contain data blocks. Some of these blocks can be empty or half full. On the next cycle, all the lanes transmit a SEP block, each one containing the number of valid bytes transmitted in the previous cycle in that lane. When using CRC, these SEP blocks also contain the 32-bit CRC for that lane over the duration of the recent frame.

Table 2. Framing Mode Packet Format of 896 Bytes Length with CRC for Line Rates > 16.375 Gbps on 16 Lanes
Lanes Data (first beat) Data (intermediate burst) Data (last beat) Control
0 8 bytes - 776 bytes sep,crc0
1 - - - sep,crc1
2 - - - sep,crc2
3 - - - sep,crc3
4 - - - sep,crc4
5 - - - sep,crc5
6 - - - sep,crc6
7 - - - sep,crc7
8 - - - sep,crc8
9 - - - sep,crc9
10 - - - sep,crc10
11 - - - sep,crc11
12 - - - sep,crc12
13 - - - sep,crc13
14 - - - sep,crc14
15 128 bytes - 896 bytes sep,crc15