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AXI Chip2Chip LogiCORE IP Product Guide (PG067)
Document ID
PG067
Release Date
2026-02-11
Version
5.0 English
Figure 1. Customization Vivado IDE for the AXI Chip2Chip Core

Chip2Chip AXI Mode
The Chip2Chip AXI Mode configuration option determines AXI Chip2Chip Master or Slave mode of operation.
AXI Clocking Mode
The AXI Chip2Chip core can be configured with either Independent or Common Clock domains

The Independent Clock configuration allows you to implement unique clock domains on the AXI interface and FPGA I/Os. The AXI Chip2Chip core handles the synchronization between clock domains. Both the AXI interface and FPGA I/Os can also be maintained in a single clock domain. The AXI Chip2Chip core can be used to generate a core optimized for a single clock by selecting the Common Clock option.

Chip2Chip AXI4-Lite Mode
The Chip2Chip AXI4-Lite Mode configuration option determines AXI4-Lite Master or Slave mode of operation, as shown in the following table. When AXI4-Lite interfacing is not required, this configuration option should be set to “None.”
Table 1. AXI4-Lite Configuration Options
Chip2Chip Mode Chip2Chip AXI4-Lite Options
Mode AXI4 Interface Mode AXI4-Lite Interface
Master FPGA Slave Master Slave
Slave Master
None None
Slave FPGA Master Master Slave
Slave Master
None None
AXI Data Width
The AXI Data Width user option allows the width of AXI data to be configured. Valid settings for the AXI Data Width are 32, 64 and 128. This setting must be maintained the same in both Master and Slave AXI Chip2Chip cores.
AXI ID Width
The AXI ID provides an identification tag for the group of signals in the channel. AXI ID is supported for all write and read channels. ID width can be configured from 0 to 12 bits. This setting must be maintained the same in both Master and Slave AXI Chip2Chip cores.
AXI WUSER Width
AXI WUSER defines sideband information that can be transmitted with the write data channel. The valid range for WUSER width is from 0 to 4 bits. This setting must be maintained the same in both Master and Slave AXI Chip2Chip cores.
Important: Because theAXI Chip2Chip core supports a maximum ID width of 12, ensure that the propagated ID width to the AXI Chip2Chip core is less than or equal to 12. This commonly happens in Zynq 7000 device systems because the ID width of GP ports is 12. To avoid this scenario, the ID widths of the GP ports can be compressed by modifying the Static Remap option available in the processing system.
Tip: The AXI ID Width of the AXI Chip2Chip Slave core should match the AXI ID Width of the AXI Chip2Chip Master core.
Important: In IP integrator, the AXI ID and WUSER Width of the interconnect are automatically propagated to the AXI Chip2Chip Master core. However for the AXI Chip2Chip Slave core, you have to override the AXI ID Width and WUSER Width so that it matches the parameters of the Master AXI Chip2Chip core.
Chip2Chip PHY Type
The Chip2Chip PHY type can be set to either “SelectIO SDR”, “SelectIO DDR”, "Aurora64B66B" or “Aurora 8B/10B.” This setting must be maintained the same in both Master and Slave AXI Chip2Chip cores.

The AXI Chip2Chip IP does not instantiate an Aurora core, but it does provide an interface to connect to it. Be sure to select the right device when simulating, synthesizing, and implementing the example design of AXI Chip2Chip with the PHY Type set as Aurora.

Chip2Chip PHY Width
The Chip2Chip PHY Width configuration determines I/Os used for device-to-device SelectIO interfacing. This setting must be maintained the same in both Master and Slave AXI Chip2Chip cores. The following table provides the mapping between Chip2Chip PHY width and the number of input and output I/Os used with the selected option.
Table 2. FPGA SelectIO Utilization
AXI Data Width Chip2Chip PHY Type 1 Chip2Chip PHY Width Number of Output I/Os Number of Input I/Os
32 SelectIOSDR Compact 4:1 2 19 19
Compact 2:1 31 31
SelectIODDR Compact 4:1 2 10 10
Compact 2:1 16 16
Compact 1:1 29 29
64 SelectIOSDR Compact 4:1 2 26 26
Compact 2:1 45 45
SelectIODDR Compact- 4:1 2 14 14
Compact 2:1 23 23
Compact 1:1 42 42
  1. SelectIOPHY interface routes the clock with the data pins.
  2. Compact 4:1 is not supported when the AXI4-Lite Interface is enabled for the core.
Chip2Chip PHY Frequency
When using the SelectIOFPGA interface, the Chip2ChipPHY implements the mixed-mode clock manager (MMCM) on the PHY input clocks. MMCMs are used for clock phase alignment, clock slew reduction, and for compensating clock buffer delays. For common clock AXI Chip2Chip Slave operations,the m_aclk_out output is generated from the MMCM. The Chip2Chip PHY Frequency provides the clock frequency parameter to the MMCM.

For Common clock, C_SELECTIO_PHY_CLK must be set to the s_aclk frequency. For Independent clock, C_SELECTIO_PHY_CLK must be to set to the axi_c2c_phy_clk frequency. This setting must be maintained the same in both Master and Slave AXI Chip2Chip cores.

Important: In IP integrator, the PHY Frequency parameter is automatically computed based on the clock frequency of the port connected to axi_c2c_phy_clk (Master Independent clocking configuration) or axi_c2c_selio_rx_ *_clk_in* port(s) (Slave configuration). In Master Common clocking configuration, the frequency of the connected AXI clock is propagated to the PHY Frequency parameter.
No. of Lanes
Number of Lanes to be selected in Aurora IP when configuring the C2C Core with Aurora Mode.
Enable Link Handler
By enabling this option the core handles the graceful exit of the pending AXI transactions. When it is selected, there is an additional port ‘axi_c2c_lnk_hndlr_in_progress’.