User Parameters - User Parameters - 5.0 English - PG067

AXI Chip2Chip LogiCORE IP Product Guide (PG067)
Document ID
PG067
Release Date
2026-02-11
Version
5.0 English

The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).

Table 1. User Parameters
Vivado IDE Parameter/Value 1 User Parameter/Value 1 Default Value
AXI Mode

C_MASTER_FPGA

  • - 1
  • - 0
 1

Clocking mode

  • - Independent
  • - Common

C_COMMON_CLK

  • - 0
  • - 1
 0

AXI4-Lite Mode

  • - None
  • - Master AXI4-Lite
  • - Slave AXI4-Lite

C_INTERFACE_TYPE

  • - 0
  • - 1
  • - 2
 0

Data Width

  • -32
  • -64
  • -128

C_INTERFACE_TYPE

  • - 32
  • - 64
  • - 128
 32
Address Width Range (32 to 64) C_AXI_ADDR_WIDTH Range (32 to 64) 32
ID width Range (0 to 24)

C_AXI_ID_WIDTH

*Applicable for master mode

C_M_AXI_ID_WIDTH

*Applicable for slave mode Range (0 to 24)

 6
WUSER Width Range (0 to 4)

C_AXI_WUSER_WIDTH

*Applicable for master mode

C_M_AXI_WUSER_WIDTH

*Applicable for slave mode Range (0 to 4)

 4

PHY Type

  • - SelectIO SDR
  • - SelectIO DDR
  • - AURORA6466B
  • - AURORA8 B10 B

C_INTERFACE_TYPE

  • - 0-
  • 1
  • - 2
  • - 3
 1

PHY Clock Frequency (in MHz) Range (40 to 400)

 C_SELECTIO_PHY_CLK Range (40 to 400) 100

Enable Differential Clock

  • - false
  • - true

C_USE_DIFF_CLK

  • - 0
  • - 1
 0

Enable Differential IO Data

  • - false
  • - true

C_USE_DIFF_IO

  • - 0
  • - 1
 0

Enable Link Handler

  • - false
  • - true

C_EN_AXI_LINK_HNDLR

  • - 0
  • - 1
 0

For faster example design simulation

  • - false
  • - true
 C_SIMULATION 0
  1. Parameter values are listed in the table where the Vivado IDE parameter value differs from the user parameter value. Such values are shown in this table as indented below the associated parameter.