Upgrading in the Vivado Design Suite - Upgrading in the Vivado Design Suite - 5.0 English - PG067

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

Document ID
PG067
Release Date
2026-02-11
Version
5.0 English

This section provides information about any changes to the user logic or port designations that take place when you upgrade to a more current version of this IP core in the Vivado Design Suite.

Parameter Changes

There are no parameter changes.

Port Changes

There are no port changes.

For designs using Aurora as the PHY type, the following ports were added:

  • aurora_do_cc
  • aurora_pma_init_in
  • aurora_pma_init_out
  • aurora_init_clk
  • aurora_mmcm_not_locked
  • aurora_reset_pb
Note: The support for interoperability between different IP versions is not maintained.