Throughput and Latency - Throughput and Latency - 5.0 English - PG067

AXI Chip2Chip LogiCORE IP Product Guide (PG067)
Document ID
PG067
Release Date
2026-02-11
Version
5.0 English

The AXI Chip2Chip core throughput is governed by the configured AXI Data Width, operating frequency of AXI interface, PHY interface and PHY Width mode (also called compact ratio or muxing ratio). The following empirical formula provides guidance on the maximum theoretical throughput that the core can provide for the AXI Read/Write channel with a known overhead.

Throughput = ((1 – overhead factor) * AXIDataWidth * PHYFrequency) / MuxingRatio

The overhead factor is dependent on the PHY interface characteristics and PHY-specific Chip2Chip core overhead. The following documents contain more information about the PHY interface characteristics:

  • Aurora 8B/10B LogiCORE IP Product Guide (PG046)
  • Aurora 64B/66B LogiCORE IP Product Guide (PG074)
  • High Speed SelectIO Wizard LogiCORE IP Product Guide (PG188)
  • SelectIO Interface Wizard LogiCORE IP Product Guide (PG070)

The following example assumes the overhead factor is 0.25, the AXIDataWidth is 32, the PhyFrequency is 100, and the MuxingRatio is 1.

Throughput = ((1 – 0.25) * 32 * 100)/1 = 2400 Mb/s

The above calculation assumes the AXI clock frequency and PHY clock frequency ratio is within 0.75 to 1.25 range for the Physical interface to be effectively used.

The MuxingRatio depends on the PHY width selection:

  • MuxingRatio is 1 when PHY Width is selected as Compact 1–1
  • MuxingRatio is 2 when PHY Width is selected as Compact 2–1
  • MuxingRatio is 4 when PHY Width is selected as Compact 4–1
Important: The AXI Chip2Chip core should be configured so the theoretical throughput is higher than the average traffic sent over the link.

The following table lists the latencies and throughput measurements on the AXI4 interface of the Chip2Chip Master core with SelectIOinterface. The measurements were taken with simultaneous read and write operations. The measurement setup issued up to four AXI4 outstanding transactions. The AXI (system) clock frequency was set to 100 MHz, and ALEN was set to 16 beats. The measured latency can have up to 5-10% variation and does not account for system latencies outside of the AXI Chip2Chip core.

Table 1. Throughput and Latency for AXI4 Interface of the AXI Chip2Chip Master Core
Features Latencies (AXI Clocks) Throughput (Mb/s)
AXI Data Width PHY Width (Number of I/Os) PHY Clock / PHY Type 1 AW_Valid to B_Valid AR_Valid to R_Valid Write Data Channel Read Data Channel
32-bit Compact 4-1 (38) 200 MHz / SDR 77 44 1190 1280
Compact 2-1 (32) 150 MHz / DDR 69 47 1770 1920
Compact 1-1 (58 2 ) 100 MHz / DDR 57 42 2350 2550
64-bit Compact 4-1 (28) 150 MHz / DDR 95 59 1780 1920
Compact 2-1 (46) 100 MHz / DDR 77 51 2370 2560
  1. The number of I/Os is determined by the PHY Type and PHY Width configurations. See Table 2 for more details.
  2. Common Clock mode of operation was selected for configurations having the same PHY clock and AXI clock frequencies (100 MHz).