Revision History - Revision History - 5.0 English - PG067

AXI Chip2Chip LogiCORE IP Product Guide (PG067)
Document ID
PG067
Release Date
2026-02-11
Version
5.0 English

The following table shows the revision history for this document.

Section Revision Summary
02/11/2026 Version 5.0
Product Specification Added Aurora 8B10B Support for Versal Devices section.
Resets Updated this section.
05/11/2022 Version 5.0
Product Specification Updated Table 1 with axi_c2c_config_error_out signal information.
11/24/2020 Version 5.0
Design Flow Steps Added the Simulation Speed Up section.
04/04/2018 Version 5.0
C_SIMULATION Added description for C_SIMULATION.
10/04/2017 Version 5.0
General updates
  • Added a new feature for handling pending AXI Transactions in-case of Link Failure.
  • Removed the Disable De-Skew and Disable Clock Shift option from the GUI.
  • Updated the core to 5.0, as the IP is modified to calculate the correct lanes/ IO count for certain combinations of Data Width, ID Width and Address Width.
04/05/2017 Version 4.3
Chip2Chip PHY Frequency Added separate parameters to set the ID widths in the slave configuration.
11/18/2015Version 4.2
General updates Added support for UltraScale+ architecture-based devices
09/30/2015 Version 4.2
General updates Enabled support for UltraScale Architecture based devices that are using Aurora physical layer interface.
04/01/2015 Version 4.2
User Parameters
  • Enhanced support for 128 data width (in aurora interface mode) and 64 address width.
  • Added User Parameters Table.
11/19/2014 Version 4.2
Product Specification Updated ”Throughput and Latency.”
Designing with the Core Added more details to “Auto-Negotiation.”
10/01/2014 Version 4.2
General Updates
  • Added support for Aurora 8 B/10 B IP core.
  • Clarified maximum ID width restrictions as it relates to Zynq 7000 devices.
04/02/2014 Version 4.2
General updates
  • Updated core to v4.2.
  • Added details about integrating the core with the AMD Aurora IP core using the Vivado IP integrator.
Appendix Included new port details in " Migrating and Upgrading."
Designing with the Core Added clocking, reset and interface connectivity details for connecting to the Aurora IP core
12/18/2013 Version 4.1
General Updates Added support for Aurora interface.
10/02/2013 Version 4.1
General updates
  • Updated Core to v4.1.
  • Added support IP integrator.
  • Changed all signals and ports to lowercase.
Example Design Added chapter
Test Bench Added Chapter
Appendix Added The Migrating and Updating
03/30/2013 Version 4.0
General Updates
  • Updated core to v4.0.
  • Added support for Vivado Design Suite.
  • Removed support for ISETM Embedded Development Kit (EDK).
12/18/2012 Version 3.0
General Updates
  • Updated core to v3.00 a and ISE Embedded Development Kit (EDK) to v14.4.
  • Added support for AXI4-Lite.
Appendix C Added Debugging.
10/25/2012 Version 2.1
Overview Corrected typo in Figure 1.
10/16/2012 Version 2.0
General updates AMD initial release. Updated core to v2.00 a and ISE Embedded Development Kit (EDK) to v14.3.
07/25/2012 Version 1.0
General Updates XilinxTM Beta release.