Interrupt and Status Signals - Interrupt and Status Signals - 5.0 English - PG067

AXI Chip2Chip LogiCORE IP Product Guide (PG067)
Document ID
PG067
Release Date
2026-02-11
Version
5.0 English

The following table describes the interrupt and status signals for the AXI Chip2Chip core.

Table 1. Interrupt and Status Signals
Name Direction Description
axi_c2c_link_status_out Output Link Status: Asserted when Link Detect FSM is in the SYNC state. Deasserted when either the Master or Slave AXI Chip2Chip core is under reset or when the Link Detect FSM is not in the SYNC state.
axi_c2c_link_error_out Output Link Error Interrupt: Asserted when the AXI Chip2Chip Slave core is reset during normal operations. This signal is valid only in Master mode.
axi_c2c_multi_bit_error_out Output Multi-bit Error Interrupt: When asserted, this interrupt indicates multiple bits are received with errors in the Master or Slave AXI Chip2Chip core. For theSelectIO interface, a multi-bit error is determined during deskew operations and indicates failure of those operations.
axi_c2c_config_error_out Output Configuration Error Interrupt: Applicable only when Aurora is selected as the FPGA interface for the core. When asserted, this interrupt indicates that Link Detect FSM has failed due to a configuration mismatch of Master and Slave AXI Chip2Chip cores.
axi_c2c_m2s_intr_in Input Level Interrupt signaling from AXI Master to AXI Slave. The interrupt input should not toggle too frequently. It should stay high or low for a sufficient amount of time, for reliable transfer.
axi_c2c_s2m_intr_out Output Level Interrupt signaling from AXI Slave to AXI Master. The output values change only when a change in interrupt data is observed. If the interrupts on Slave instance changes too frequently, then Master instance cannot be able to keep a track of it.
axi_c2c_m2s_intr_out Output Level Interrupt signaling from AXI Master to AXI Slave. The output values change only when a change in interrupt data is observed. If the interrupts on Master instance changes too frequently, then Slave instance cannot be able to keep a track of it.
axi_c2c_s2m_intr_in Input Level Interrupt signaling from AXI Slave to AXI Master. The interrupt input should not toggle too frequently. It should stay high or low for a sufficient amount of time for reliable transfer.
  1. All the output ports belonging to the interrupt and status signals are synchronous to the *_aclk clock domain.