Interrupt Signals - Interrupt Signals - 5.0 English - PG067

The AXI Chip2Chip core allows level interrupts to be communicated through a high-priority internal channel. Interrupts can be independently communicated between AXI Masters and AXI Slaves. On detecting a value change in the interrupt inputs, the AXI Chip2Chip Master core initiates a high-priority transfer to update the interrupt outputs of the AXI Chip2Chip Slave core. Similarly, on detecting a value change in the interrupt inputs, the AXI Chip2Chip Slave core initiates a high-priority transfer to update the interrupt outputs of the AXI Chip2Chip Master core. At system level, you should ensure that the interrupt level is not changed until it reaches the other end. It is recommended to ensure the interrupt level remains stable for a minimum of 16 cycles to ensure recognition at the receiving end (master/slave). For example, an interrupt that is set on Slave instance might be unset only when it has reached the master instance. Interrupts might not be transferred properly if they toggle at a faster rate.

The AXI Chip2Chip Master core also generates interrupts for link error conditions. Interrupt signals are asserted by the AXI Chip2Chip Master core. For this, the error conditions detected in the AXI Chip2Chip Slave core are communicated to the Master device through a high-priority internal channel.

The following interrupt signals are supported in the AXI Chip2Chip Master core:

Link Error Interrupt

Asserted when the AXI Chip2Chip Slave core is reset during normal operation. For more details on Link Error Interrupt, see Resets.

Multibit Error Interrupt

When asserted, a Multibit Error interrupt indicates multiple bits are received in error in the Master or Slave AXI Chip2Chip. For the SelectIO interface, a multibit error is determined during deskew operations and indicates deskew operation failure.

Configuration Error Interrupt

The Configuration Error Interrupt is set when a mismatch is detected between the Master and Slave AXI Chip2Chip core configurations.

After being asserted, interrupt flags can be cleared only with a reset.

Graceful Exit in case of Link Failure

The Chip2Chip core supports completion of pending AXI Transactions, when there is a link failure between Chip2Chip master and Chip2Chip slave (when the core is generated by enabling the Enable Link Handler option).

Note: Note: Select this feature only when there is a need to complete the pending AXI Transactions between master and slave (for example: Cable unplug between master / slave).

Link Handler Operation for Chip2Chhip Master Core

Link handler keeps track of the AXI Transactions and performs the following actions when the link goes down:

1. *_awready is gracefully pulled to low, that is, no new requests are accepted from the AXI Master.
2. It accepts the exact number of pending data transactions and later the *_wready is gracefully pulled to low.
3. Link Handler sends out the write response as "Slave Error" for the pending transactions to the AXI Master.
4. *_arready is gracefully pulled to low, that is, no new requests are accepted from the AXI Master.
5. It the generates the remaining number of pending read transactions to the AXI Master. Once there are no-more pending read transactions the *_rvalid is gracefully pulled low. Here, the Read Response are the Error Response and the Read Data are all zeros.

Link Handler Operation for Chip2Chhip Slave Core

Link handler keeps track of the AXI Transactions and performs the following actions when the link goes down:

1. *_awvalid is gracefully pulled to low, that is, no new write requests are issued to the AXI Slave.
2. It generates the remaining number of pending write data transactions to the AXI Slave. Once there are no-more pending write transactions the *_wvalid is gracefully pulled to low. The Write Data and the Strobe are all zeros.
3. *_arvalid is gracefully pulled to low, that is, no new read requests are issued to the AXI Slave.
4. It accepts the exact number of pending data transactions and later the *_rready is gracefully pulled to low, when there are no more pending requests.

For more information, see Link Handler Sequence.