Hardware Testing - Hardware Testing - 5.0 English

Hardware Testing - Hardware Testing - 5.0 English - PG067

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

Document ID

PG067

Release Date

2026-02-11

Version

5.0 English

The following figure shows the hardware testing setup for the AXI Chip2Chip core.

Figure 1. AXI Chip2Chip Hardware Testing Setup

The AXI Chip2Chip core with a SelectIO FPGA interface has been hardware validated on a KC705 board using a Kintex 7 FPGA with –1 speed grade (325T). The setup uses two additional FMC loopback cards. The following table provides configuration details for the AXI Chip2Chip core and the frequency achieved by using this setup with the SelectIOinterface.

Table 1. Hardware Testing Configuration with a SelectIO FPGA interface
Features			I/Os Used	PHY Clock (MHz)
AXI Data Width	Chip2Chip PHY Type	Chip2Chip PHY Width	Single Ended [HR I/O Banks]	LVCMOS_25 I/O [Unterminated]
32-bit	SelectIOSDR	Compact 4:1	38	200
	SelectIODDR	Compact 1:1	58	100
	SelectIODDR	Compact 2:1	32	150
	SelectIODDR	Compact 4:1	20	150
64-bit	SelectIODDR	Compact 2:1	46	100
64-bit	SelectIODDR	Compact 4:1	28	150
The AXI (system) clock frequency was set to 100 MHz, and the Common Clock mode of operation was selected for configurations having the same PHY clock and AXI clock frequencies (100 MHz).

In addition, AXI Chip2Chip Reference Design for Real-Time Video Application Note (XAPP1160) provides a setup demonstrating real-time video traffic across Kintex 7 FPGA boards (KC705) and Zynq 7000 devices. This setup uses the AXI Chip2Chip core for connectivity across the FPGA using LPC/HPC connector cables.

The AXI Chip2Chip Reference Design for Real-Time Video Applications Application Note (XAPP1216) demonstrates real-time video traffic between two Kintex 7 FPGA KC705 evaluation boards or one KC705 board and one Zynq 7000 ZC706 evaluation board. The AXI Chip2Chip core provides connectivity between the two boards using SMA data connector cables.